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VLSI architecture of dynamically reconfigurable hardware-based cipher

Content Provider	IEEE Xplore Digital Library
Author	Mitsuyama, Y. Andales, Z. Onoye, T. Shirakawa, I.
Copyright Year	2001
Description	Author affiliation: Dept. of Inf. Syst. Eng., Osaka Univ., Japan (Mitsuyama, Y.)
Abstract	This paper describes a 64-bit block, 128-bit key, dynamically reconfigurable hardware-based cipher, called Chameleon, in which two 32-cell, 8-context dynamically reconfigurable hardware units are employed to generate new subkeys for each of the 16 iterations in the encryption/decryption process. The proposed architecture has been implemented by the 0.6 /spl mu/m CMOS 3LM technology, using 65.6 K transistors and attaining a maximum throughput of 317.5 Mbps. The new approach demonstrates distinctive features of enhanced complexity and flexibility dedicatedly for embedded encryption/decryption applications in mobile computing.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	734
Ending Page	737
File Size	478343
Page Count	4
File Format	PDF
ISBN	0780366859
DOI	10.1109/ISCAS.2001.922342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Cryptography Registers Hardware Computer architecture CMOS technology Information systems Systems engineering and theory Throughput Mobile computing
Content Type	Text
Resource Type	Article

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