NDLI: A 3.3-V analog front-end chip for HomePNA applications

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A 3.3-V analog front-end chip for HomePNA applications

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An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors

New current-mode sense amplifiers for high density DRAM and PIM architectures

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A 3.3-V analog front-end chip for HomePNA applications

Content Provider	IEEE Xplore Digital Library
Author	Jaeyoung Shin Joongho Choi Jinup Lim Sungwon Noh Namil Baek Jong-Hyeong Lee
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Seoul, South Korea (Jaeyoung Shin)
Abstract	In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-/spl mu/m CMOS technology and consumes power dissipation of 150 mW at a 3.3-V supply voltage.
Sponsorship	IEEE Circuits & Syst. Soc
Starting Page	698
Ending Page	701
File Size	431773
Page Count	4
File Format	PDF
ISBN	0780366859
DOI	10.1109/ISCAS.2001.922333
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-06
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters Filters Pulse amplifiers CMOS technology Physical layer Pulse generation Driver circuits Gain control Power dissipation Voltage
Content Type	Text
Resource Type	Article

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