NDLI: Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation

Content Provider	IEEE Xplore Digital Library
Author	Mahapatra, N.R. Garimella, S.V. Takeen, A.
Copyright Year	2000
Description	Author affiliation: Dept. of Comput. Sci. & Eng., State Univ. of New York, Buffalo, NY, USA (Mahapatra, N.R.)
Abstract	This paper presents a new framework called gate triggering for systematically minimizing glitch power dissipation in static CMOS ICs. It is based on the idea that glitches can be effectively minimized by triggering logic evaluation at a gate only when all of its inputs have stablized. For this purpose, to every potentially glitchy gate (or a suitable subset of such gates) is added a small amount of control logic, which, when enabled triggers logic evaluation at the gate. A clocked delay chain is employed to generate enable signals at the proper times for all gates to be triggered. We present six specific techniques based on gate triggering that differ in the type of control logic and the way it is used to control a gate. These techniques have varying effectiveness and area and timing overheads, which we analyze in detail. Application of these techniques to test circuits yields promising results.
Starting Page	537
Ending Page	540
File Size	803101
Page Count	4
File Format	PDF
ISBN	0780354826
DOI	10.1109/ISCAS.2000.856384
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-28
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Logic gates CMOS logic circuits Very large scale integration CMOS technology Logic devices Timing Circuit testing Propagation delay Computer science
Content Type	Text
Resource Type	Article

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