NDLI: Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic

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Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic

Content Provider	IEEE Xplore Digital Library
Author	Min Zhao Sapatnekar, S.S.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Min Zhao)
Abstract	In this paper two problems on domino logic synthesis are addressed. A mapping method that maps the complementary logic cones independently when AND/OR logic is to be implemented and together using dual-monotonic gates in the case of XOR/XNOR logic, is proposed. The results show up to 28.9% improvement in area and always show the same or better performance in delay over existing approaches. Then a 0-1 integer programming formulation is provided for the output phase assignment problem for domino logic. It considers the cost difference between two polarities and enables a standard linear programming package to be used to solve the problem. The results show up to 41.0% improvement in area.
Starting Page	309
Ending Page	312
File Size	412011
Page Count	4
File Format	PDF
ISBN	0780354826
DOI	10.1109/ISCAS.2000.856323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-28
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic programming Network synthesis Signal synthesis Costs Logic design Logic circuits Signal mapping Delay Linear programming Logic gates
Content Type	Text
Resource Type	Article

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