Please wait, while we are loading the content...
Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jinn-Shyan Wang Pei-Lung Lin Wern-Ho Sheen Duo Sheng Yu-Ming Huang |
| Copyright Year | 2000 |
| Description | Author affiliation: Inst. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan (Jinn-Shyan Wang) |
| Abstract | The design of a compact high-symbol-rate adaptive equalizer IC for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is presented in this paper. Although the HIPERLAN defines a slowly time-varying multi-path fading-channel system, the Inter-Symbol Interference (ISI) problem is still very severe since its data rate is up to 23.5 Mbps. An Adaptive Decision Feedback Equalizer (ADFE) is selected to overcome this problem, however, the FIR filters of the ADFE require high hardware cost for complex-number computation. In this work, we select the sequential architecture to reduce the hardware cost. The penalty of adopting the sequential architecture is that several internal clocks with a much higher operating frequency (235 MHz) and the corresponding high-speed components are required. In order to generate internal clocks, we embed an All Digital Phase-Locked Loop (ADPLL) in this chip. Meanwhile, the design of high speed multipliers and adders are achieved based on the combination of PTL, CPL, and CPL-TG CMOS logic circuits. Finally, our ADFE chip is designed in a 3.3 V 0.35 /spl mu/m CMOS technology with only 3/spl times/2.8-mm/sup 2/ core area and 1 W power dissipation. |
| Starting Page | 265 |
| Ending Page | 268 |
| File Size | 428372 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780354826 |
| DOI | 10.1109/ISCAS.2000.856312 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-05-28 |
| Publisher Place | Switzerland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Adaptive equalizers Hardware Computer architecture Clocks CMOS technology High speed integrated circuits Local area networks Telecommunication standards Time varying systems Interference |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|