NDLI: New metrics for architectural level power performance evaluation

Content Provider	IEEE Xplore Digital Library
Author	Lihong Jia Yonghong Gao Tenhunen
Copyright Year	2000
Description	Author affiliation: Electron. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden (Lihong Jia)
Abstract	In this paper, we present new metrics to evaluate the performance of VLSI circuits with regards to the power consumption in the architectural level from the system point of view. One advantage of the new metrics is that the metrics not only calculate the power consumption itself but also evaluate the "low power possibility" of the architectures from the system point of view; another advantage is that the metrics consider the effects of the process technology and it can be used to evaluate the power consumption performance in the future advanced VLSI technology. Specially, we point out that reducing power supply voltage to reduce the power consumption will become less and less efficient in the deep submicron regime and thus the architecture-driven voltage scaling low power design approach will not work as well as in the previous technology.
Starting Page	549
Ending Page	552
File Size	431144
Page Count	4
File Format	PDF
ISBN	0780354826
DOI	10.1109/ISCAS.2000.856387
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-28
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Power supplies Throughput Circuits Very large scale integration Laboratories Low voltage Costs Silicon System performance
Content Type	Text
Resource Type	Article

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