NDLI: K-2 High-performance and low-Power SRAMs design in nano-scale CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Zhang, K.X.
Copyright Year	2007
Description	Author affiliation: Intel Corp., Santa Clara (Zhang, K.X.)
Abstract	Summary form only given. Static random access memory (SRAM) is key to today's high-performance and low-power VLSI system design. Among various embedded memory technologies, SRAM is able to provide the highest performance while maintaining low standby power consumption. As Moore's law drives the CMOS technology feature size well below 100 nm regime, there are many new technology and design challenges facing today's SRAM development, including cell stability scaling and power management. In this presentation, the state-of-the-art CMOS technology scaling will be first examined. Key scaling challenges along with technology innovations such as uniaxial strain Si technology will be discussed. Then, the scaling of the SRAM cell design will be evaluated in light of the technology scaling. Various design techniques, e.g., the use of dynamic multi-VCC, in mitigating the scaling difficulties in read stability and write margin will be presented. Power reduction techniques will also be discussed from both process and design perspectives, including transistor design and use of dynamic sleep transistors. Design implementation based on the state-of-the-art CPUs will also be presented.
Starting Page	2
Ending Page	2
File Size	76217
Page Count	1
File Format	PDF
ISBN	9781424411313
DOI	10.1109/ICASIC.2007.4415545
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Random access memory Stability SRAM chips Very large scale integration Energy consumption Moore's Law Energy management Technology management Technological innovation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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