NDLI: Important technologies of mix-clustered block cipher coprocessor

Content Provider	IEEE Xplore Digital Library
Author	Tao Meng Yan Zhang Zi-bin Dai
Copyright Year	2007
Description	Author affiliation: Inf. Eng. Univ., Zhengzhou (Tao Meng; Yan Zhang; Zi-bin Dai)
Abstract	Adopting Coarse-grain reconfigurable technology, 8 reconfigurable cells are designed. With these reconfigurable cells, 30 block ciphers, which include RijndaeL DES, TWOFISH, IDEA, can be realized; Separated data and sub-key register files are designed, and the Auto-Increment Access Mode is put forward. With this mode, the size of instruction RAM can be reduced a lot, and the flexibility of processing is also increased; Five-stage pipelines of whole architecture and two-stage pipelines of function cell are designed, and when it is fabricated on 0.18 um CMOS cells, core work-frequency is 312.5 MHz; Bypassing is adopted to resolve data hazards, and Speculation is adopted to resolve control hazards; Auto-Copied Threading Mode is put forward to improve threading-Level Parallelism. In this mode, speeds processing Rijndael, DES, IDEA are 1379.2 Mbps, 800 Mbps, 563.3 Mbps.
Starting Page	942
Ending Page	945
File Size	253841
Page Count	4
File Format	PDF
ISBN	9781424411313
DOI	10.1109/ICASIC.2007.4415787
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coprocessors Arithmetic Pipelines Hazards Logic CMOS process Size control Application specific integrated circuits Registers Field programmable gate arrays
Content Type	Text
Resource Type	Article

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