NDLI: An 8.3-GHz dual-modulus divide-by-31/32 prescaler using enhanced phase switching

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Table of contents

K-1 The RF-CMOS story: From university research to industry mainstream

K-2 High-performance and low-Power SRAMs design in nano-scale CMOS technology

K-3 The challenge of design flow integration and its impact on complex system design

K-4 Video compression LSI: Past, present, and future trends

K-5 Challenges for consumer electronics for the 21st century

T1 Design of integrated RF front-ends in submicron and deep submicron CMOS technologies

T2 A/D converters for wireless communication in nanometer CMOS

T3 SOC design flow case study: Design a video processing pipeline

T4 Inductance extraction and compact modeling of inductively coupled interconnects in the presence of process variations

T5 What makes Moore’s law continue? — Recent advances in semiconductor

Electrostatic Discharge (ESD) and latchup in advanced semiconductors

Software defined cognitive radios

SOC design challenges for embedded systems

Design of a dynamic memory access scheduler

A self-control structure for pipeline control

A novel dynamic scheduling algorithm of data hazard for embedded processor

A novel framework for fast embedded face detection system

A microarchitecture of clustered superscalar processor

A novel VLSI architecture for 2-D discrete wavelet transform

ASIC design of low-power reconfigurable FFT processor

Multiple-precision subword-parallel multiplier using correction-value merging technique

Design and implement of high fan-in logic in high-speed circuit

Research and implement a low-power configurable embedded processor for 1024-point fast fourier transform

Design of a fully pipelined single-precision floating-point unit

High-speed baud-rate clock and data recovery

Low leakage dynamic circuits with dual threshold voltages and dual gate oxide thickness

Power management with fuzzy decision support system

Power management by brain emotional learning algorithm

Multi-level signaling for energy-efficient on-chip interconnects

A power optimized carry generation logic Implementation using input pattern based area reduction technique for Adder Structures

Modified modular inversion algorithm for VLSI implementation

A design flow for clock controller hard-macro generation

General purpose multi-channel signal generator based on Xilinx Virtex II Pro FPGAs

Design of heterogeneous MPSoC on FPGA

Design and realization of a system simulator

PAFESD: Process algebras for electronic system designs

On Extended Graph-Based Rewiring Technique

Design space exploration in multi-objective hierarchical SOC design

Analog design of a Radial Basis Function network

Single-phase adiabatic flip-flops and sequential circuits using improved CAL circuits

a new type of high-performance low-power low clock-swing TSPC flip-flop

A low-power adiabatic CAM based on dual transmission gate adiabatic logic

Research of adiabatic multiplier based on CTGAL

A low clock swing, power saving and generic technology based D flip-flop with single power supply

An energy-efficient power-gating adiabatic circuits using transmission gate switches

Power estimation technique for Reed-Muller logic circuits

Fast bit permutation instruction based on Omega+Omega network

An FPGA configuration circuit used for fast and partial configuration

Adiabatic tree multipliers using modified booth algorithm

Research on low power design in SOC by using charge-recovery technology

± 1.2V High frequency four quadrant current multiplier

Design theory and fabrication process integration of 32nm node Si, Ge and Si1-xGex vertical dual carrier field effect transistor SOC for switching and communication applications

Design and implementation of a high-speed reconfigurable multiplier

The use of WAGA to search the best polarity of XNOR/OR logic

A Contribution to the Discrete Z-Domain Analysis of ADPLL

A 250MHz optimized distributed architecture of 2D 8x8 DCT

Power reduction through specific instruction scheduling based on Hardware/Software Co-Design

Montgomery multiplier based on secondary booth encoded algorithm

A new design of mixed-voltage I/O buffers with low-voltage-thin-oxide CMOS process

Implementing elliptic curve cryptography on Nios II processor

Dynamic priority assignment based task scheduling for battery-powered portable systems

A high-speed dual field arithmetic unit and hardware implementation

Updating strategy based architecture for reference picture management in H.264/AVC

An application-specific memory partitioning method for low power

Efficient architecture for two-dimensional discrete wavelet transform based on lifting scheme

Low-power implementations of DSP through operand isolation and clock gating

Design and test of a digital system based on a CMOS 0.35μm logarithmic pixel for time of flight measurement applications

A modified golumbic algorithm for permutation graphs in VLSI

Research on new implementation method of chaotic model based on FPGA

Trends in high speed ADC design

A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references

A digital-background TIADC calibration architecture and a fast calibration algorithm for timing-error mismatch

A 10-b 80Ms/s time-interleaved pipeline ADC using partially opamp sharing Scheme

Improved digital calibration technology in a 12-b, 40-MS/s pipelined ADC

Low-power CMOS folding and interpolating ADC with a fully-folding technique

A high precisions stereo Analog-to-Digital converter

Design of a small-area current steering CMOS D/A converter based on a novel layout technique

A low power and low 1/f-noise transconductance for the input stage of a current sense A/D converter

A novel double-sampling sigma-delta modulator architecture for broadband applications

A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters

A second-order low power current-mode continuous-time sigma-delta modulator

Low phase noise CMOS voltage-controlled oscillators

A fractional-N frequency synthesizer with a wide-band small gain-Fluctuation VCO for mobile DTV applications

Low jitter design for ring oscillator in Serdes

1.25Gb/s low jitter dual-loop clock and data recovery circuit

Design a 4GHz PLL for wireless receiver

Design of low jitter adaptive-bandwidth charge pump PLL with passive filter

A 1.2V low-jitter PLL for UWB

Fractional-N phase locked loop design and applications

A Frequency Stabilization Circuit for The Voltage Controlled Ring Oscillator

A Programmable Spread Spectrum Clock Generation

Design of a High Precision and High stability Oscillator with External Synchronization

A virtual orthogonal output direct digital frequency synthesizer design and implementation

MIMO RFIC Transceiver Designs for WLAN Applications

The design of a new spiral inductor balun used in RF/MW based on 0.13μm CMOS process

The scheme and key components design of W-band coherent doppler velocity radar front-end

Fully integrated passive UHF RFID tag with temperature sensor for environment monitoring

Noise figure in UWB systems

A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization

A fully integrated CMOS UWB transmitter

ESD and latchup: Computer aided design (CAD) tools and methodologies for today and future VLSI designs

SCR-type ESD protection circuit for RFICs

A class-AB square-root domain biquad filter based on floating gate MOS transistors

A novel ESD protection circuit for ultra-deep-submicron low power mixed-signal IC designs

An integrated channel noise-based true random number generator

A pseudo-Gaussian filter and sigma-delta modulator for IEEE 802.11a/b/g transmitter

A 0.13μm CMOS Gm-C LPF for UWB receiver

Transimpedance amplifier with PDCM and AGC

An Ultra-Wideband CMOS low noise amplifier For 3–5 GHz UWB wireless receivers

A switching-band CMOS low-noise amplifier for 6–11GHz MB-OFDM UWB wireless radio system

CMOS dual-wideband low-noise amplifier with notch filter for 3.1GHz–10.6GHz ultra-wideband wireless receiver

A 0.18um 3.3mW double-balanced CMOS active mixer

Design and optimization of highly linear CMOS low noise amplifiers via geometric programming

A 2.4GHz highly linear class C power amplifier in 0.18 μ m CMOS technology

A low noise high linearity CMOS upconversion mixer

Power efficient circuit design

CMOS chopper amplifier for monolithic magnetic hall sensor

Optimum design of a fully differential 12bit 100MS/s sample and hold module with over 77dB SFDR

The design of internal load independent compensation for current-mode DC-DC converters

A novel compact soft-start circuit with internal circuitry for DC-DC converters

Power recovery circuit for battery-less TPMS

Novel low-power DC-DC converter with high-efficiency charge pump circuits

The design and optimization of gain-boosted OTA for high speed and high accuracy sample and hold amplifier

A novel common-mode sensing circuit with large input swing for Op-AMP with common-mode feedback

A low-power, high-speed open-loop residue amplifier for pipelined ADCs with digital calibration

A capacitor-mismatch-insensitive switch-capacitor amplifier for Pipeline ADC

An ultra-low current mode amplifier aiming at biosensor applications

A 1.3GHz wideband successive detection logarithmic amplifier

CMOS Anti-Self-Biasing effect and its implication in analog/RF circuit design

A low noise CMOS charge sensitive preamplifier for MEMS capacitive accelerometer readout

A Novel data-sparsification method for radiation detector readout ASICs

A low-power low-cost digital readout circuit for dual-band infrared sensor array

A high efficient analog charge delay line for high performance CMOS readout integrated circuits with TDI function

A novel MOSFET-only current reference with multiple temperature compensations

A curvature compensated CMOS bandgap voltage reference for high precision applications

A new fully differential second generation current conveyor

A bandgap reference circuit with nominal value adjustable

A technology compensated current reference in standard CMOS

A CMOS voltage reference without resistors for ultra-low power applications

Design and analysis of high power supply rejection CMOS bandgap voltage reference

A programmable CMOS voltage reference based on a proportional summing circuit

Design of a novel voltage comparator circuitry based on trimming technique

A dual-path three-stage VCO with wide tuning range

A new wireless receiver topology

A 2.5 GHz low phase noise LC VCO in 0.35μm SiGe BiCMOS technology

A high precision CMOS bandgap reference with second-order curvature-compensation

Common-mode rejection ratio analysis of fully differential class AB two-stage op-amp with and without common-mode feedback circuit

Effect of OTA’s major nonidealities to passive equivalent circuit model of the alternatively structured higher performance OTA-based floating inductor

A 2.5Gb/s low noise CMOS transimpedance amplifier

A new CMOS electronically tunable current conveyor based on translinear circuits

A low-voltage 2.45GHz CMOS linear power amplifier

A calibration architecture for improving the performance of time-interleaved ADC

Power efficient high speed switched current comparator

A 8-bit 125-MSample/s pipelined ADC

A highly linear wide range continuous tuning CMOS OTA

A tri-section stepped impedance bandpass filter with harmonic suppression

Design and implementation of high-efficiency and low-power DC-DC converter with PWM/PFM modes

All CMOS temperature, supply voltage and process independent current reference

A 2.5-Gb/s half-rate clock and data recovery circuit with a digital quadricorrelator frequency detector

An adaptive slope compensation circuit for buck DC-DC converter

A novel SCR for ESD protection in ICs

A 57mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach

An 8.3-GHz dual-modulus divide-by-31/32 prescaler using enhanced phase switching

Class AB low voltage high linearity mixer design

System design of a low noise, low offset instrumentation amplifier with chopper stabilization

An analysis and implementation of common mode feedback in high-speed fully differential op-amp

A multi-phase self-sensing clock generator for hybrid DPWM application

Design of a broadband LNA for TV tuner

An efficient CMOS operational amplifier for driving large capacitive loads

Design of a synchronizable oscillator with stable frequency

Design of a voltage comparator using for switching regulator

Optimizing approach of spiral inductors for Si-Based ICs

Design of PWM controller for monolithic boost converter

Investigation into the 12-bit DA converter

Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC

2.4GHz VCO design and tail current analysis

Studies on design of micro power consumption E/D NMOS reference source

A CMOS polyphase low-IF filter with on-chip frequency control

A dual-band fractional-N synthesizer for 3G TD-SCDMA

QSSB mixer design for MB-OFDM UWB frequency synthesizer

A high precision CMOS bandgap reference

A 2.4-GHz spur-cancelled fractional-n frequency synthesizer with PFD/DAC structure for WSN application

A 20mW 200MHz CMOS continuous-time sigma-delta modulator with 5MHz signal bandwidth and 12 bits of resolution

A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter

Novel CMOS second-generation current-controlled conveyor base on modified differential-pair input-stage

A design of temperature-compensated CMOS voltage reference sources with a small temperature coefficient

Continuous-time sigma-delta modulator design for low power communication applications

A high-performance memory storage architecture for MP@HL MPEG2 decoder chip

An Auto-exposure algorithm for detecting high contrast lighting conditions

Design and implementation of twin transport stream demultiplexor in HDTV decoder

Cost-effective VDMOS for PDP scan driver IC

Optimized Scheme of Frequency De-interleaving of China Digital Television Terrestrial Transport Standard

Design of a configurable system-on-chip for audio application

Precision imaging for biosensing (INVITED)

An efficient programmable engine for interpolation of multi-standard video coding

An ASIC implementation of MPEG audio decoders

A 41mW VGA@30fps quadtree video encoder for video surveillance systems

A parallel serial filtering mixed advanced ID interpolation architecture for AVS

An application specific matrix processor for signal subspace based speech enhancement in noise robust speech recognition applications

Implementation of fast Huffman decoding algorithm

A Novel reconfigurable VLSI architecture for motion estimation

An Efficient algorithm for intra-prediction mode selection in H.264

Cost efficient propagate partial SAD architecture for integer motion estimation in H.264/AVC

VLSI design for de-blocking filter of H.264 decoder

A high-performance VLSI architecture for CABAC decoding in H.264/AVC

An improved inter frame error concealment in H.264/AVC

Unequal error protected transmission with dynamic classification in H.264/AVC

A partial scramble scheme for H.264 video

A novel CML-based synchronization algorithm for IR-UWB communications

Adaptive automatic gain control using hybrid gamma parameters for frame-based OFDM receivers

The research and design of reconfigurable cipher processing architecture targeted at block cipher

A novel timing acquisition scheme based on energy detection for UWB communications

Optimization of symbol timing recovery for DTMB receivers

Efficient DFT based carrier recovery for satellite DVB receiver

An MBOK-UWB SoC transceiver in 0.181μm CMOS technology

Simulation design of a new 3.1–10.6GHz single-full-band non-carrier pulse-based Ultra Wideband (1-UWB) system

VLSI implementation of an AES algorithm resistant to Differential Power Analysis attack

A parallel co-processor architecture for block cipher processing

FPGA design and implementation of carrier synchronization for DVB-S2 demodulators

A reconfigurable modular arithmetic unit for public-key Cryptography

Mixed bus width architecture for low cost AES VLSI design

Design and optimized implementation of the SHA-2(256, 384, 512) hash algorithms

A reconfigurable and ultra low-cost VLSI implementation of SHA-1 and MD5 functions

Design and VLSI implementation of a security ASIP

A novel baseband-processor for LF RFID tag

A 13.56 MHz adiabatic smart card / RFID

A novel passive UHF RFID transponder with space division Anti-collision Algorithm

Research of design and verification of fieldbus communication control ASIC FBC100-H1

Design of a low-power digital core for passive UHF RFID sensor

NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing

Research of an image map encoding algorithm on frame buffer

The decoder of trellis code implemented by CMOS analog circuits

Third type interconnection architecture for the 3D MP-SoC design

Design and implementation of crypto-based interleaver for viterbi encoder and decoder using turbo codes

Bandwidth-reusable CDMA NoC with flexible codeword assignment

Study on hybrid switching mechanism in network on chip

RS(23,17) decoder for UWB

Digital decimation filter design and simulation for delta-sigma ADC with high performance

A VLSI implementation of a FEC decoding system for DTMB (GB20600–2006) standard

Service dependency graph for HW/SW interfaces modeling: The motion-JPEG case study

Design, implementation and testing of an IEEE 802.11 b/g baseband chip

A mode correlation-based fractional pixel motion estimation for H.264 video coding

Important technologies of mix-clustered block cipher coprocessor

System level modeling of WiMAX SoC system

A new high throughput VLSI architecture for H.264 transform and quantization

design of cyclic correlator for channel estimation in DTMB system Yuan Chen Yun Chen An Pan Jun Chen Xiaoyang Zeng State Key Lab of ASIC and System, Fudan University, Shanghai 201203, China

Hybrid synchronous sampling tracking loop for IR-UWB communications

A unified IDCT architecture for multi-standard video codecs

System-on-chip design for a statistical decoder

The digital hardware design of the passive electron tag based on the protocol of ISO/IEC 14443-A

Design of a synchronous-rectified buck bootstrap MOSFET driver for voltage regulator module

Testing methods for integrated circuit of phase locked loops

An improved high level test synthesis algorithm

A hardware approach to reconfigurable lossless real-time tracer

Improved low power full scan BIST

Low-Power built-in logic block observer realization for BIST applications

Hardware/software co-verification scheme for MSTP ASIC

An on-chip monitor for hot carrier induced degradation

A new soft IP core for online-testing and fault-tolerant structures

A novel oscillation-based BIST for ADCs

Design and implementation of DFT strategy for an industrial communications and control SoC

A Novel Multi-Capture Scan Testing

Development of Non-contact Physiological Motion Sensor on CMOS Chip and Its Potential Applications

Embedded SRAM circuit design technologies for a 45nm and beyond

Array and high voltage path design for SONOS flash memory

Experiments on reducing standby current for compilable SRAM using hidden clustered source line control

Design of NOR flash memory cells with high speed programming by utilizing an asymmetric Silicide(TiSi2) Drain

A new self-oscillation loop for MEMS vibratory gyroscopes

Modeling of temperature characteristics for metal-ferroelectric-insulator-semiconductor devices

The nonswitching dielectric layer thickness dependence of the channel current in MFIS-FET

Design theory and fabrication process integration of 65nm and 32nm Node Si vertical dual carrier field effect transistor CPU for parallel arrays of computers.

Compact model of surface potential in strong inversion channel

A novel low power bus coding technique for nanometer technology

A fixed-outline floorplanning method

Hierarchical thermal model using gauss-seidel method in floorplanning

Ordered single chain tree a new coding scheme for standard cell placement

Floorplanning with constraint extraction based on interconnecting information analysis

A new multi-layer global routing flow for congestion elimination

Thermal-aware incremental floorplanning for 3D ICs

Performance maximized interlayer via planning for 3D ICs

Stochastic based extended krylov subspace method for power/ground network analysis

Yield impact from physical design at advanced technology nodes

Local refinement method for optimizing clock tree topology

G-Tree: Gravitation-direction-based rectilinear Steiner minimal tree construction considering bend reduction

How to process a multi million gate ASIC layout in 21 hours

Leakage power reduction through dual Vth assignment considering threshold voltage variation

A novel equivalent circuit and parameter extraction for on-chip spiral inductors

An analytical method for the calculation of self and mutual inductance on RF circuit

Parametric analysis of multiple interconnects via canonical reduced order modeling

A novel model for an integrated rf CMOS schottky diode

An improved nonlinear empirical model applied to RF SOI LDMOSFET

Monte carlo simulation of Cu-resistivity considering size-effects

Investigation into sub-threshold performance of double-gate accumulation-mode SOI PMOSFET

Threshold voltage modeling of deep-submicron double-gate fully-depleted SOI MOSFET

An efficient transformation method for DFRM expansions

Sequential equivalence techniques for high performance design

Verification techniques imposed upon design of a standard cell based dsp dedicated to cochlear implant

A technique to avoid combination feedback loop and long critical path in resource sharing

An efficient sequential equivalence checking framework using Boolean Satisfiability

A thermal-aware ILP-based algorithm in behavioral synthesis

A new resource constrained scheduling method based on dynamic combination of genetic algorithm and ant algorithm

VLSI power wiring noise analysis using MOR method

An efficient preconditioning scheme for fast hierarchical method in 3-D capacitance extraction of IC interconnect

Modeling and simulation of an open-loop architecture ADC

A fast-simulation model for post-layout SRAM

The cycle accurate DSP model design based on SystemC

A SystemC simulation modeling approach for allocating task precedence graphs to multiprocessors

Verifying dynamics of mixed-signal circuits with random noise using statistical Petri Net

A new efficient modified-Newton method and its application in time-domain circuit simulation

Automated design method for parameters optimization of CMOS analog circuits based on adaptive genetic algorithm

Sensitivity analysis of interconnect lines based on differential quadrature method

DME-based clock routing in the presence of obstacles

Dynamic power consumption of distributed RLC trees

A compressed BiCGStab algorithm for power and ground network analysis

Analysis of self-heating effect and breakdown characteristics in partial SOI LDMOS with multi silicon windows

A network-on-Chip system-level simulation environment supporting asynchronous router

Implementation of a C-to-SystemC synthesizer prototype

A novel high level testability synthesis method based on PSA

The research and implement of an advanced function coverage based verification environment

Abstraction of word-level polynomial function from waveform polynomial descriptions

VLSI implementation of reconfigurable SRRC filters with automatic code generation

An algorithm for detecting logic implementation mode

A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs

Behavioral model of data acquisition system by using Simulink

Complexity reduction for SOPC-based H.264/AVC coder via sum of absolute difference

A novel placement algorithm for symmetrical FPGA

Simulation and performance analysis of network on chip architectures using OPNET

Design and simulation of a torus structure and route algorithm for network on chip

Heterogeneous design methodology with configurable regular topology set for scalable Network-on-Chip designs

Quantum-dots cellular automata comparator

A power-aware adaptive routing scheme for network on a chip

Improving NOC performance through a new data-transfer technique

Revising link capacity adjustment scheme for ASIC applications

A practical IP quality measurement framework

A watermarking technique for hard IP protection in post-layout design level

A SystemC-based hardware platform design of Network-on-a-Chip

Low power design with multi-Vdd and voltage islands (Abstract)

Sleep transistor sizing in power gating designs

Leakage aware design for next generation’s SOCs

Clock tree synthesis for low power and low susceptibility to variation

Passivity-preserving model order reduction of linear time-varying macromodels

Statistical worstcase interconnect modeling based on non-normal distributed process variations for nanometer era

Hardware acceleration for sparse fourier image reconstruction

A high-frequency DC-DC converter based power amplifier for direct RF carrier generation

Dual reference frequencies for low spur and low phase noise fractional- N frequency phase locked loop

A new ESD-aware power amplifier design method

Inductorless Design of Wireless CMOS Frontends

Design of highly efficient and linear class E SiGe power amplifier for highly-integrated multifunctional wireless transmitters

2005 6th International Conference on ASIC

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2nd International Conference on ASIC

An 8.3-GHz dual-modulus divide-by-31/32 prescaler using enhanced phase switching

Content Provider	IEEE Xplore Digital Library
Author	Dapeng Li Min Cai
Copyright Year	2007
Description	Author affiliation: South China Univ. of Technol., Guangzhou (Dapeng Li)
Abstract	A differential 8.3-GHz dual-modulus divide-by-31/32 prescaler is presented in this paper. Compared to the conventional prescaler using a serial of synchronous and asynchronous counters, the phase-switching technique enable only the first divide-by-two stage working at the full speed, maximizing operating frequency and reducing the overall power consumption. Enhanced 8-to-1 phase-switching technique and current-mode logic (CML) are utilized to achieve high operating speed at a comparatively low level of power consumption. The proposed prescaler will be fabricated in HEJIAN 0.18-mum mixed-mode and RFCMOS 1.8 V/3.3 V 1P6M process. It operates over a wide range from 200 MHz to 10 GHz, in which it typically draws a 7.3 mA current at 8.3 GHz from 1.8 V supply.
Starting Page	620
Ending Page	623
File Size	212538
Page Count	4
File Format	PDF
ISBN	9781424411313
DOI	10.1109/ICASIC.2007.4415707
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Robustness Circuits Timing Frequency conversion Frequency synthesizers CMOS technology CMOS process Signal generators Synchronous generators
Content Type	Text
Resource Type	Article

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