NDLI: Congestion and performance driven full-chip scalable routing framework

Content Provider	IEEE Xplore Digital Library
Author	Hailong Yao Yici Cai Xianlong Hong Qiang Zhou
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing (Hailong Yao; Yici Cai; Xianlong Hong; Qiang Zhou)
Abstract	Timing is one of the emerging issues in deep sub-micrometer technology which has great influence on the circuit performance. This paper presents a novel full-chip scalable routing framework, which considers the routing congestion and the circuit performance simultaneously. The framework features the fast pattern and framed shortest path global router and a maze-based congestion-driven detailed router. We also introduce a criticality-driven least flexibility prior net ordering technique which assigns timing-critical nets higher priority for performance concern. Then nets are routed one by one according to their priorities and the routing resource is updated immediately after each routing, which results in very accurate resource estimation. We have tested our routing framework on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing framework. The experimental results are very promising
Starting Page	856
Ending Page	859
File Size	974006
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611440
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Timing Circuit optimization Circuit testing Very large scale integration Electronic design automation and methodology Benchmark testing Clocks Frequency Integrated circuit interconnections
Content Type	Text
Resource Type	Article

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