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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zheying Li Shuo Li Minjie Ma Li Li |
| Copyright Year | 2005 |
| Description | Author affiliation: Inf. Sch., Beijing Union Univ. (Zheying Li) |
| Abstract | This paper described a modeling method for consistency checking of IP blocks used in design of a mixed-signal SoC (MS SoC). The consistency includes four points in the MS SoC design to guarantee the IP blocks suitable for applications. The four points are architecture matching, parameter matching, time matching, and frequency matching. Based on the signal flow graph (SFG), the MS SoC constructed by different IP blocks can be a signal processing system including analog part and digital part. After adding two new definitions on an edge function, which is used for the description of the parameter consistency, a set of nodes and edges function becomes the base of the checking model. The checking model can describe the consistency of the architecture and the parameter including time and frequency matching |
| Starting Page | 1066 |
| Ending Page | 1070 |
| File Size | 659599 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780392108 |
| DOI | 10.1109/ICASIC.2005.1611485 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-10-24 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analog circuits Digital circuits Frequency Manufacturing Design engineering Microelectronics Information technology Flow graphs Digital signal processing Filters |
| Content Type | Text |
| Resource Type | Article |
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