NDLI: A low quiescent current and reset time adjustable power-on reset circuit

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2005 6th International Conference on ASIC

Volume 2 - 2005

2005 6th International Conference on ASIC Proceedings

Table of contents

Conference committee

Welcome to ASICON 2005

Keynote Speech (K-1) Opportunity and challenge for IC development in mainland of China

Keynote Speech (K-2) Design Automation in the "Late-CMOS" Age

Keynote Speech (K-3) The Secret Analog Revolution

Keynote Speech (K-4) ASICs in a Global Economy; The Industrialization of the Semiconductor Industry

Tutorial Session Index

A ow-Phase- oise CMOS Ring Oscillator with ifferential Control

A fully integrated 1.2-GHz CMOS phase-locked loop

A curvature-compensated bandgap reference with improved PSRR

A low-voltage low-power CMOS sample-and-hold circuit

A low noise CMOS wideband PLL with a new AAC LC-VCO

A high-accuracy BiCMOS constant current charge circuit

A novel digital soft-start circuit for DC-DC switching regulator

A low quiescent current and reset time adjustable power-on reset circuit

A novel design of supply voltage selector

The design of a novel feedforward control circuit for DC-DC converter

Pulsed multilevel current drive circuitry with LDMOS for monolithic deformable mirror

An improved charge pump with high efficiency for low voltage operations

A fully integrated 0.18-/spl mu/m CMOS low noise amplifier for 2.4-GHz applications

A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers

Design of a DLL-gated 1.25G clock synthesizer for impulse UWB system

High performance current comparator with gain boosting structure

A CMOS RF bandpass filter based on the active inductor

High efficient rectifier circuit eliminating threshold voltage drop for RFID transponders

A low phase noise VCO using enhanced LC resonator in an single-chip ASK receiver

A design of high speed AGTL+ output buffer

Design and verification of CMOS HSTL buffers - YF/spl I.bar/HSTL018

A 5GHz CMOS monolithic fractional-N frequency synthesizer

Low noise operational amplifier design with current driving bulk in 0.25/spl mu/m CMOS technology

CMOS-based gas sensor: SoC approach

Implement any fractional order multilayer dynamics associative neural network

Test modification and compression technique for reducing total test volume with dictionary data

A current sensing circuit for IDDQ testing

Out of band interference measurement of negative feedback amplifiers

A new test data compression/decompression scheme to reduce SOC test time

Measurement techniques for smart sensor interfaces implemented in CMOS technology

Design and implementation of DFT strategy in ASIC design of resilient packet ring

A low-cost BIST scheme for ADC testing

A way of enhancing test quality and restraining the increase of test cost for deep sub-micron integrated circuits

The implementation method about verifying to VLIW DSP

A P1500-compliant wrapper and TAM controller co-design scheme

Study on analyzing and modeling of delay activity for digital circuit

A novel method for the construction of self-dual circuits

FBDD: a folded logic synthesis system

FPGA design on saturation correction in radar digital IF receiver

FPGA implementation of image rotation using modified compensated CORDIC

An optimized adder accumulator for high speed MACs

Design and FPGA implementation of OLT for EPON

Design and implementation of reconfigurable AES IP core using FPGAs

FPGA implementation of alterable parameters RSA public-key cryptographic coprocessor

Application of DRFM in high frequency ground wave radar

Pre-processing speech signals in FPGAs

Design of a 16-bit real time stack processor in FPGA

FPLACEMENT: new placement software for FPGA with bus resources

VLSI dynamically reconfigurable hardware for finite state machine design and analyses

Research on generating the constants T[i] of MD5 algorithm based on FPGAs

Hardware design of real-time offline Jawi character recognition chip using discrete wavelet transform

Design with fluctuations of device characteristics - TCAD can be of any help?

Deterministic skip lists in analog topological placement

A fast and stable force-directed placement with implicit buffer planning

An efficient algorithm for hexagon/triangle placement by extending the application of the sequence pair representation

Congestion and performance driven full-chip scalable routing framework

Interconnect delay optimization using a novel hybrid insertion strategy

Power/ground network aware and row-based solutions to the crosstalk driven routing problem

A fast placement approach for large scale modules based on less flexibility first principles

An ECO algorithm for resolving OPC and coupling capacitance violations

A new FPGA packing algorithm based on the modeling method for logic block

3D placement algorithm considering vertical channels and guided by 2D placement solution

Design tools for 3D mixed mode placement

Area optimization in deep sub-micron VLSI design

New metal fill considerations for nanometer technologies

FPGA placement using genetic algorithm with simulated annealing

A universal hierarchical FPGA partitioning algorithm

A research on optimum-searching quadratic optimization for very large-scale standard cell placement

A datapath routing algorithm using bit regularity extraction

Analog constraints extraction based on the signal flow analysis

Hexagon/triangle packing using improved least flexibility first principle algorithm

VLSI Floorplan Based on Less Flexibility First Principle and Linear Programming

A shortest-path-search algorithm with symmetric constraints for analog circuit routing

Hardware-software cosynthesis of multitask MPSoCs with real-time constraints

A technique to exploit memory locality for fast instruction set simulation

Transition traversal coverage estimation for symbolic model checking

Automatic instruction generation for application specific co-processor

Virtual embedded operating system for hardware/software co-design

FSM decomposition for power gating design automation in sequential circuits

Industrial scale formal verification using concurrent GSTE

BDD minimization based on genetic tabu hybrid strategy

Mapping of IP cores to network-on-chip architectures based on communication task graphs

Domain coverage metric for validation

Feedback driven high level synthesis for performance optimization

Implementation of a flexible development platform for simultaneous support of software and hardware development flow

RTL property checking technology based on ATPG and ILP

Verification of a configurable processor core for system-on-a-chip designs

Extraction of feedback information from circuit netlists

A fast algorithm for power optimization using multiple voltages in data path synthesis

Datapath verification with SystemC reference model

RTL satisfiability solving using an ATPG based approach

Frontend model generation for SAT-based property checking

VLSI interconnect signal analysis using a projection framework method

A systemC-based NoC simulation framework supporting heterogeneous communicators

A delay metric for VLSI interconnect

Gate delay estimation based on close-ended line model

Compact model for RF CMOS differential transformers up to 30 GHz

A novel method to simulating transient response of interconnects

Applying formal techniques in simulation-based verification

Energy oriented optimization of dynamic management strategy for scratch-pad memory

SFG modeling for consistency checking of mixed-signal SoC

Power property analysis for CMOS integrated circuits

A structural behavioural modelling approach for top-level analogue mixed-signal functional verifications

A Structural Behavioural Modelling Approach for Top-Level Analogue Mixed-Signal Functional Verifications

Experimental studies on SAT-based test pattern generation for industrial circuits

Modeling lossy substrates with direct boundary element method

Minimum error based affine arithmetic for variational timing analysis

Modeling of capacitor array mismatch effect in embedded CMOS CR SAR ADC

Interconnect delay and slew computation with the first three moments

Broyden method for the self-consistent solution of Schrodinger and Poisson equations

Novel ESD protection design methodology and latchup prevention for a 0.5-/spl mu/m CMOS ASIC library

Stability Analysis of C- C Converter sing Behavioral Modeling Technique

Mixed-signal system modeling methodology with VHDL-AMS

Macromodel of switched-capacitor sigma-delta modulator

I-V characteristic of BJMOSFET based on SOI

Two dimensional device simulation and fabrication of mesa SOI vertical dual carrier field effect transistor with effective channel length of 30nm for switching ASIC and SOC

Fast mode decision algorithm in H.264 for video communications

A pilot based EM channel estimator for OFDM systems

Impact of process variation on soft error vulnerability for nanometer VLSI circuits

A novel heuristic approach for bounding maximum and minimum leakage power

A mixed design flow for FPGA prototyping of design with scan circuits

A hierarchy watermarking technique for IP core protection

Structuring analog fractance circuit for 1/2 order fractional calculus

Integrated device and circuit simulation of "dual carrier field effect transistor" and "three dimensional field effect transistor" with effective channel length of 5-20nm and their ASIC and SOC

CMP service for prototyping and low volume production

The Signal Processing System Design of General Weather Radar Based on ASIC

Signal integrity timing closure of million gates SOC platform

Circuit design of an improved approximate squaring function

A novel hardware implementation of MP3 decoder for low power and minimum chip size

Fitting SOC miniature MEMS reconfigurable antenna

An instruction-level analytical power model for designing the low power systems on a chip

Any fractional order H type analog fractance circuit

Volume 1 - 2005

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

2nd International Conference on ASIC

A low quiescent current and reset time adjustable power-on reset circuit

Content Provider	IEEE Xplore Digital Library
Author	Lai Xinquan Yu Weixue Ligang Cao Yu
Copyright Year	2005
Description	Author affiliation: Inst. of Electron. CAD, Xidian Univ., Xi'an (Lai Xinquan; Yu Weixue; Ligang; Cao Yu)
Abstract	Based on the power-up/power-down control, the paper describes a low quiescent current and reset time adjustable power-on reset (POR) circuit, which is integrated in a regulator. Compared with the conventional RC reset circuit, it can provide more accurate reset pulse at slow power up and twinkling power down. And when the chip works properly, parts of the power-on reset circuit are shut down, then the quiescent current of the POR is reduced by 12muA. In addition, the power-on reset time can be adjusted based on different applications
Starting Page	559
Ending Page	562
File Size	954625
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611392
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Regulators Detectors Microprocessors Capacitors Threshold voltage Resistors Coupling circuits Pulse circuits Delay effects Pulse generation low quiescent current POR reset time
Content Type	Text
Resource Type	Article

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