NDLI: A technique to exploit memory locality for fast instruction set simulation

Content Provider	IEEE Xplore Digital Library
Author	Wei Qin Bo Hu
Copyright Year	2005
Description	Author affiliation: Boston Univ., USA (Wei Qin)
Abstract	To verify software and system functionality during the design process of complex SoCs, designers routinely use instruction set simulators (ISSs) as high level processor models. Typically, an ISS needs to simulate billions of target instructions to verify a single task of the system in design, which is a very time-consuming process. Therefore, the simulation speed of ISSs has become one important concern of SoC designers. In this paper, we present a new technique to improve the speed of ISSs. Specifically, we focus on the translation of memory addresses between the target memory space and the host memory space. Such translation is performed by a hash table in many ISS implementations. To accelerate the translation, we introduce a software cache called translation buffer (TB) to cache the hashing results for quick future access. With properly chosen TB sizes, our implementation effectively exploits the abundant locality inherent in the memory footprints of real-world application programs and greatly reduces the overall address translation overhead. We integrated the technique into three popular ISSs and achieved a 15-32% improvement in simulation speed.
Starting Page	915
Ending Page	918
File Size	1325975
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611459
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Application software Acceleration Program processors Hardware Electronic design automation and methodology Registers Read-write memory Software systems Process design
Content Type	Text
Resource Type	Article

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