NDLI: A practical runtime test method for parallel lattice-gas automata

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Proceedings The International Conference on Application Specific Array Processors

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A practical runtime test method for parallel lattice-gas automata

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Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7)

A practical runtime test method for parallel lattice-gas automata

Content Provider	IEEE Xplore Digital Library
Author	Squier, R. Steiglitz, K.
Copyright Year	1990
Abstract	The authors describe a test method for lattice-gas automata of the type introduced by U. Frisch et al. (1986). The test method consists of inserting test patterns into the initial state of the automaton and using a graphics display to detect errors. The test patterns are carefully constructed limit cycles that are disrupted by errors occurring at any level of the simulator system. The patterns can be run independently to test the system for debugging purposes, or they can be run as sub-simulations embedded in a larger lattice-gas simulation to detect faults at runtime. The authors describe the use of this method on a prototype parallel machine for lattice-gas simulations, and discuss the range of systems that can make use of this type of test method. The test patterns detect all significant one-bit errors. Included are experimental results indicating that multiple bit errors are unlikely to escape detection.<>
Starting Page	782
Ending Page	793
File Size	626563
Page Count	12
File Format	PDF
ISBN	0818690895
DOI	10.1109/ASAP.1990.145512
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Automatic testing Automata System testing Graphics Displays Limit-cycles Debugging Fault detection Virtual prototyping
Content Type	Text
Resource Type	Article

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