NDLI: Application specific VLSI architectures based on De Bruijn graphs

Please wait, while we are loading the content...

Proceedings The International Conference on Application Specific Array Processors

Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94)

Proceedings of International Conference on Application Specific Array Processors (ASAP '93)

[1992] Proceedings of the International Conference on Application Specific Array Processors

Proceedings of the International Conference on Application Specific Array Processors

[1990] Proceedings of the International Conference on Application Specific Array Processors

Calculus of space-optimal mappings of systolic algorithms on processor arrays

A processor-time minimal systolic array for transitive closure

Systolic array implementation of nested loop programs

The bit-serial systolic back-projection engine (BSSBPE)

A database machine based on surrogate files

Systolic architectures for decoding Reed-Solomon codes

Mapping high-dimension wavefront computations to silicon

Systolic architecture for 2-D rank order filtering

Scheduling affine parameterized recurrences by means of

The Logic Description Generator

Recursive algorithms for AR spectral estimation and their array realizations

Analysing parametrised designs by non-standard interpretation

Systolic VLSI compiler (SVC) for high performance vector quantisation chips

Extensions to linear mapping for regular arrays with complex processing elements

Design of run-time fault-tolerant arrays of self-checking processing elements

GRAPE: a special-purpose computer for N-body problems

Building blocks for a new generation of application specific computing systems

Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor

Massively parallel architecture: application to neural net emulation and image reconstruction

A real-time software programmable processor for HDTV and stereo scope signals

Mapping algorithms onto the TUT cellular array processor

A 3-D wafer scale architecture for early vision processing

Algorithmic mapping of neural network models onto parallel SIMD machines

Implementation of systolic algorithms using pipelined functional units

Array processing on finite polynomial rings

The RAP: a ring array processor for layered network calculations

Linear arrays for residue mappers

A fault-tolerant two-dimensional sorting network

Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

Digit-serial DSP architectures

PASIC. A sensor/processor array for computer vision

An analog VLSI array processor for classical and connectionist AI

Systolic two-port adaptor for high performance wave digital filtering

An improved multilayer neural model and array processor implementation

Reconfiguration of FFT arrays: a flow-driven approach

Towards the automated design of application specific array processors (ASAPs)

Fault-tolerant array processors using N-and-half-track switches

Domain flow and streaming architectures

An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation

Digit-serial VLSI microarchitecture

CMOS VLSI Lukasiewicz logic arrays

Dynamic systolic associative memory chip

ASP modules: building-blocks for application-specific massively parallel processors

Designing specific systolic arrays with the API15C chip

A prototype for a fault tolerant parallel signal processor

Byte-serial convolvers

A VLSI architecture for simplified arithmetic Fourier transform algorithm

Fine-grain system architectures for systolic emulation of neural algorithms

Programming environment for a line processor-SYMPATI-2

A feedback concentrator for the Image Understanding Architecture

A design methodology for fixed-size systolic arrays

A formal design methodology for parallel architectures

A multiple-level heterogeneous architecture for image understanding

Application specific VLSI architectures based on De Bruijn graphs

A graph-based approach to map matrix algorithms onto local-access processor arrays

Application-specific coprocessor computer architecture

Embedding pyramids in array processors with pipelined busses

Implementation of ANN on RISC processor array

Systolic-based computing machinery for radar signal processing studies

A systolic array for nonlinear adaptive filtering and pattern recognition

Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing

The design of a high-performance scalable architecture for image processing applications

Testing a motion estimator array

Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problem

Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithm

Bit-level systolic algorithm for the symmetric eigenvalue problem

A practical runtime test method for parallel lattice-gas automata

A systolic array programming language

Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7)

Application specific VLSI architectures based on De Bruijn graphs

Content Provider	IEEE Xplore Digital Library
Author	Pradhan, D.K.
Copyright Year	1990
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA (Pradhan, D.K.)
Abstract	The author provides an overview of various key features of De Bruijn graph-based VLSI architectures. The advantages of De Bruijn architectures over such other architectures as cube and shuffle-exchange are discussed. Important differences between De Bruijn interconnects and others are also described. The evolution of the De Bruijn interconnect is described. The FFT architecture and the Viterbi decoder for convolutional codes are examined in detail. The issues of routing and fault tolerance are addressed.<>
Starting Page	628
Ending Page	640
File Size	471427
Page Count	13
File Format	PDF
ISBN	0818690895
DOI	10.1109/ASAP.1990.145498
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Computer architecture Fault tolerance Distributed computing Computer networks Concurrent computing Application software Proposals Robustness Communication networks
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in