NDLI: CMOS VLSI Lukasiewicz logic arrays

Content Provider	IEEE Xplore Digital Library
Author	Mills, J.W. Daffinger, C.A.
Copyright Year	1990
Description	Author affiliation: Dept. of Comput. Sci., Indiana Univ., Bloomington, IN, USA (Mills, J.W.; Daffinger, C.A.)
Abstract	Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements. The authors have designed and performed preliminary tests on a series of CMOS VLSI LLAs whose cells perform Lukasiewicz implication ( to ). The authors describe the LLA architecture and its relationship to cellular automata, describe the CMOS VLSI implementation of versions LL9 and LL10 and their initial characterization, and report on the results obtained by programming LL9 and LL10 as fuzzy function recognizers, the first step in designing more general function units such as expert systems and neural networks. Initial test results showed that the LLAs implemented the notch function linearly, but with a slope that varied from that of the ideal function. Trimming the LLA inputs and outputs is expected to result in a typical error of less than 2%, and a mean error of less than 0.5%.<>
Starting Page	469
Ending Page	480
File Size	539026
Page Count	12
File Format	PDF
ISBN	0818690895
DOI	10.1109/ASAP.1990.145483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic arrays Very large scale integration CMOS logic circuits Performance evaluation Testing Analog computers Binary trees Computer architecture Automatic programming Functional programming
Content Type	Text
Resource Type	Article

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