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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wu, C.-M. Owens, R.M. Irwin, M.J. |
| Copyright Year | 1990 |
| Description | Author affiliation: Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA (Wu, C.-M.; Owens, R.M.; Irwin, M.J.) |
| Abstract | The authors present a new template-matching algorithm with good recognition performance. However, this new algorithm exhibits a complex, four-dimensional, wavefront architecture. Thus, for VLSI implementation, reduced architectures with fewer connections and processors need to be derived. For this purpose, the authors develop a systematic reduction methodology to manually map wavefront computations from high-dimension to low-dimension. This methodology consists of seven steps. Based on this methodology, the authors derive several two-dimensional architectures which are suitable for VLSI implementation for the new template-matching algorithm and have simulated one of the architectures by using the Intel Hypercube Machine iPSC/2.< |
| Starting Page | 78 |
| Ending Page | 89 |
| File Size | 433780 |
| Page Count | 12 |
| File Format | |
| ISBN | 0818690895 |
| DOI | 10.1109/ASAP.1990.145445 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-09-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Very large scale integration Computer architecture Data flow computing Computational modeling Heuristic algorithms Computer science Flow graphs Shift registers Hypercubes |
| Content Type | Text |
| Resource Type | Article |
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