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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Benaini, A. Robert, Y. |
| Copyright Year | 1990 |
| Description | Author affiliation: LIP-IMAG, Ecole Normale Superieure de Lyon, France (Benaini, A.; Robert, Y.) |
| Abstract | The authors have designed two systolic arrays that are both time-minimal and space-minimal for Gaussian elimination and the algebraic path problem (APP), thereby establishing the systolic complexity of these two computational kernels. The systolic computation is modeled by a directed acyclic graph (DAG) with nodes corresponding to computed values and arcs denoting dependencies. The computation DAG is taken to be fixed and given. The time to compute a DAG is determined when a timing function is assigned, or scheduled, to the nodes, subject to the constraints that a node can be computed only when its predecessors (the nodes which it depends upon) have been computed at previous steps, and no processor can compute two different nodes at the same time step. For a problem of size n, the authors obtain an execution time (T(n))=3n-1 using A(n)=n/sup 2//4+O(n) processors for Gaussian elimination, and T(n)=5n-2 and A(n)=n/sup 3//3+O(n) for the APP.< |
| Starting Page | 746 |
| Ending Page | 757 |
| File Size | 590530 |
| Page Count | 12 |
| File Format | |
| ISBN | 0818690895 |
| DOI | 10.1109/ASAP.1990.145509 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1990-09-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Systolic arrays Equations Processor scheduling Timing Computational modeling Councils Gaussian processes Linear systems Transforms |
| Content Type | Text |
| Resource Type | Article |
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