NDLI: An Optimized Structure of 4H-SiC U-Shaped Trench Gate MOSFET

Content Provider	IEEE Xplore Digital Library
Author	Ying Wang Kai Tian Yue Hao Cheng-Hao Yu Yan-Juan Liu
Copyright Year	1963
Abstract	In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm²/Vs, and the specific ON-resistance and the BVwere 1.64 mΩ·cm² (VGS = 15 V, VDS = 1 V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation.
Sponsorship	IEEE Electron Devices Society
Starting Page	2774
Ending Page	2778
Page Count	5
File Size	2199350
File Format	PDF
ISSN	00189383
Volume Number	62
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates MOSFET Silicon carbide Wrapping Substrates Resistance U-shaped trench gate MOSFET (UMOSFET). 4H-SiC breakdown voltage (BV) gate-drain charge (QGd) ON-state specific resistance (RON_sp) U-shaped trench gate MOSFET (UMOSFET) gate–drain charge ( $Q_{\rm {Gd}})$ ON-state specific resistance ( $R_{\mathrm{{\scriptscriptstyle ON}}-{\rm sp}})$
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Investigation of SiC trench MOSFET with floating islands

3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field

High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

SiC Heterojunction Trench MOSFET with a Buried P-Type Pillar for the Low Gate-Drain Charge and Switching Loss

Gate Enhanced Power UMOSFET With Ultralow On-Resistance

Investigation of 3.3 kV 4H-SiC DC-FSJ MOSFET Structures

An Optimized Structure of 4H-SiC U-Shaped Trench Gate MOSFET

Similar Documents

Investigation of SiC trench MOSFET with floating islands

3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field

High-Performance Gate-Enhanced Power UMOSFET With Optimized Structure

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

SiC Heterojunction Trench MOSFET with a Buried P-Type Pillar for the Low Gate-Drain Charge and Switching Loss

Gate Enhanced Power UMOSFET With Ultralow On-Resistance

Investigation of 3.3 kV 4H-SiC DC-FSJ MOSFET Structures

An Optimized Structure of 4H-SiC U-Shaped Trench Gate MOSFET