NDLI: FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics

Content Provider	IEEE Xplore Digital Library
Author	Vita Pi-Ho Hu Ming-Long Fan Chien-Yu Hsieh Pin Su Ching-Te Chuang
Copyright Year	1963
Abstract	This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-fe metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO₂ and SiO₂/HfO₂) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM.
Sponsorship	IEEE Electron Devices Society
Starting Page	805
Ending Page	811
Page Count	7
File Size	1484366
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory FinFETs Wireless sensor networks Logic gates Degradation Dielectrics variability FinFET negative bias temperature instability (NBTI) positive bias temperature instability (PBTI) static random access memory (SRAM) surface orientation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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