NDLI: Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

Content Provider	IEEE Xplore Digital Library
Author	Alperin, M.E. Hollaway, T.C. Haken, R.A. Gosmeyer, C.D. Karnaugh, R.V. Parmantie, W.D.
Copyright Year	1966
Description	A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	61
Ending Page	69
Page Count	9
File Size	1378946
File Format	PDF
ISSN	00189200
Volume Number	20
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Titanium Silicides Very large scale integration Etching CMOS technology Manufacturing processes MOS devices Circuit testing Thickness control Random access memory
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Nonoverlapping super self-aligned device structure for high-performance VLSI

A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI

Titanium silicide interconnect technology for submicrometer DRAMs

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

A new self-aligned VLSI Isolation process using thin-metal lift-off

Quadruply Self-Aligned MOS (QSA MOS) - A New Short-Channel High-Speed High-Density MOSFET for VLSI

Circuit techniques for a VLSI memory

CMOS VLSI single event transient characterization

A reconfigurable wafer-scale memory

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

Similar Documents

Nonoverlapping super self-aligned device structure for high-performance VLSI

A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI

Titanium silicide interconnect technology for submicrometer DRAMs

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

A new self-aligned VLSI Isolation process using thin-metal lift-off

Quadruply Self-Aligned MOS (QSA MOS) - A New Short-Channel High-Speed High-Density MOSFET for VLSI

Circuit techniques for a VLSI memory

CMOS VLSI single event transient characterization

A reconfigurable wafer-scale memory

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications