NDLI: Performance Limits of CMOS ULSI

Content Provider	IEEE Xplore Digital Library
Author	Pfiester, J.R. Shott, J.D. Meindl, J.D.
Copyright Year	1966
Description	An analytic MOST model has been developed to calculate accurately threshold voltage at submicrometer dimensions and to predict the sealing limits of digital CMOS circuits. Salient results show that for 2-V power-supply voltages, channel lengths as small as 0.14 /spl mu/m for static E/E CMOS, 0.20 /spl mu/m for static E/D CMOS, 0.29 /spl mu/m for dynamic transmission-gate CMOS, and 0.45 /spl mu/m for static E/D NMOS circuits are possible. At submicrometer dimensions, CMOS offers as much as a 3:1 sealing advantage in minimum channel length which translates to a 5:1 improvement in gate delay when compared to NMOS. Thus CMOS is projected as the dominant ULSI technology, not only due to its well known large operating margins, low static-power dissipation and design flexibility but also due to markedly superior speed.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	253
Ending Page	263
Page Count	11
File Size	1797462
File Format	PDF
ISSN	00189200
Volume Number	20
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ultra large scale integration Silicon Boundary conditions Electrodes Dielectric constant Neodymium Solid state circuits Boron Gaussian processes Dielectrics and electrical insulation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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