NDLI: Scavenger: A New Last Level Cache Architecture with Global Block Priority

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Process Variation Tolerant 3T1D-Based Cache Architectures

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Optimal versus Heuristic Global Code Scheduling

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Penelope: The NBTI-Aware Processor

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

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Implementing Signatures for Transactional Memory

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Impact of Cache Coherence Protocols on the Processing of Network Traffic

Flattened Butterfly Topology for On-Chip Networks

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

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Composable Lightweight Processors

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

Emulating Optimal Replacement with a Shepherd Cache

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Scavenger: A New Last Level Cache Architecture with Global Block Priority

Content Provider	ACM Digital Library
Author	Basu, Arkaprava Chaudhuri, Mainak Kirman, Nevin Kirman, Meyrem Martinez, Jose
Abstract	Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of in- tervening misses at the last-level cache between the eviction of a particular block and its reuse can be very large, pre- venting traditional victim caching mechanisms from exploiting this repeating behavior. In this paper, we present Scavenger, a new architecture for last-level caches. Scavenger divides the total storage budget into a conventional cache and a novel victim file architecture, which employs a skewed Bloom filter in conjunction with a pipelined priority heap to identify and retain the blocks that most frequently missed in the conven- tional part of the cache in the recent past. When compared against a baseline configuration with a 1MB 8-way L2 cache, a Scavenger configuration with a 512kB 8-way conventional cache and a 512kB victim file achieves an IPC improvement of up to 63% and on average (geometric mean) 14.2% for nine memory-bound SPEC 2000 applications. On a larger set of sixteen SPEC 2000 applications, Scavenger achieves an aver- age speedup of 8%.
Starting Page	421
Ending Page	432
Page Count	12
File Format	PDF
ISBN	0769530478
ISSN	10724451
DOI	10.1109/MICRO.2007.36
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-12-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Scavenger: A New Last Level Cache Architecture with Global Block Priority

Scavenger: A New Last Level Cache Architecture with Global Block Priority (2007)

Scavenger: A New Last Level Cache Architecture with Global Block Priority (2007)

Global Priority Table for Last-Level Caches

Sampling Dead Block Prediction for Last-Level Caches

$R^{2}Cache:$ reliability-aware reconfigurable last-level cache architecture for multi-cores

Comparing last-level cache designs for CMP architectures

Last-level cache deduplication

DAPSCO: Distance-aware partially shared cache organization

Scavenger: A New Last Level Cache Architecture with Global Block Priority

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Scavenger: A New Last Level Cache Architecture with Global Block Priority