NDLI: Global Multi-Threaded Instruction Scheduling

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Process Variation Tolerant 3T1D-Based Cache Architectures

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Optimal versus Heuristic Global Code Scheduling

Global Multi-Threaded Instruction Scheduling

Revisiting the Sequential Programming Model for Multi-Core

Penelope: The NBTI-Aware Processor

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

Self-calibrating Online Wearout Detection

Implementing Signatures for Transactional Memory

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Impact of Cache Coherence Protocols on the Processing of Network Traffic

Flattened Butterfly Topology for On-Chip Networks

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Leveraging 3D Technology for Improved Reliability

Effective Optimistic-Checker Tandem Core Design through Architectural Pruning

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Time Interpolation: So Many Metrics, So Few Registers

Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors

A Framework for Providing Quality of Service in Chip Multi-Processors

A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

Composable Lightweight Processors

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

Emulating Optimal Replacement with a Shepherd Cache

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Global Multi-Threaded Instruction Scheduling

Content Provider	ACM Digital Library
Author	Ottoni, Guilherme August, David
Abstract	Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utiliz- ing the increasing transistor counts in the face of physi- cal and micro-architectural limitations. Despite this move, CMPs do not directly improve the performance of single- threaded codes, a characteristic of most applications. In or- der to support parallelization of general-purpose applica- tions, computer architects have proposed CMPs with light- weight scalar communication mechanisms [21, 23, 29]. De- spite such support, most existing compiler multi-threading techniques have generally demonstrated little effective- ness in extracting parallelism from non-scientific applica- tions [14, 15, 22]. The main reason for this is that such techniques are mostly restricted to extracting parallelism within straight-line regions of code. In this paper, we first propose a framework that en- ables global multi-threaded instruction scheduling in gen- eral. We then describe GREMIO, a scheduler built using this framework. GREMIO operates at a global scope, at the procedure level, and uses control dependence analysis to extract non-speculative thread-level parallelism from se- quential codes. Using a fully automatic compiler imple- mentation of GREMIO and a validated processor model, this paper demonstrates gains for a dual-core CMP model running a variety of codes. Our experiments demonstrate the advantage of exploiting global scheduling for multi- threaded architectures, and present gains in a detailed com- parison with the Decoupled Software Pipelining (DSWP) multi-threading technique [18]. Furthermore, our experi- ments show that adding GREMIO to a compiler with DSWP improves the average speedup from 16.5% to 32.8% for im- portant benchmark functions when utilizing two cores, indi- cating the importance of this technique in making compilers extract threads effectively.
Starting Page	56
Ending Page	68
Page Count	13
File Format	PDF
ISBN	0769530478
ISSN	10724451
DOI	10.1109/MICRO.2007.17
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-12-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Communication optimizations for global multi-threaded instruction scheduling

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