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| Content Provider | ACM Digital Library |
|---|---|
| Author | Fernández-pascual, Ricardo García-guirado, Antonio García, José M. Ros, Alberto |
| Copyright Year | 2012 |
| Abstract | Many-core tiled CMP proposals often assume a partially shared last level cache (LLC) since this provides a good compromise between access latency and cache utilization. In this paper, we propose a novel way to map memory addresses to LLC banks that takes into account the average distance between the banks and the tiles that access them. Contrary to traditional approaches, our mapping does not group the tiles in clusters within which all the cores access the same bank for the same addresses. Instead, two neighboring cores access different sets of banks minimizing the average distance travelled by the cache requests. Results for a 64-core CMP show that our proposal improves both execution time and the energy consumed by the network by 13% when compared to a traditional mapping. Moreover, our proposal comes at a negligible cost in terms of hardware and its benefits in both energy and execution time increase with the number of cores. |
| Starting Page | 1 |
| Ending Page | 19 |
| Page Count | 19 |
| File Format | |
| ISSN | 15443566 |
| e-ISSN | 15443973 |
| DOI | 10.1145/2086696.2086704 |
| Volume Number | 8 |
| Issue Number | 4 |
| Journal | ACM Transactions on Architecture and Code Optimization (TACO) |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2012-01-26 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Last-level cache Cache Distance to cache Power Static block mapping |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture Information Systems Software |
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