NDLI: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Please wait, while we are loading the content...

Message from the General Chairs

Message from the Program Chairs

Organizing Committee

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Process Variation Tolerant 3T1D-Based Cache Architectures

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Optimal versus Heuristic Global Code Scheduling

Global Multi-Threaded Instruction Scheduling

Revisiting the Sequential Programming Model for Multi-Core

Penelope: The NBTI-Aware Processor

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

Self-calibrating Online Wearout Detection

Implementing Signatures for Transactional Memory

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Impact of Cache Coherence Protocols on the Processing of Network Traffic

Flattened Butterfly Topology for On-Chip Networks

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Leveraging 3D Technology for Improved Reliability

Effective Optimistic-Checker Tandem Core Design through Architectural Pruning

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Time Interpolation: So Many Metrics, So Few Registers

Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors

A Framework for Providing Quality of Service in Chip Multi-Processors

A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

Composable Lightweight Processors

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

Emulating Optimal Replacement with a Shepherd Cache

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Content Provider	ACM Digital Library
Author	Muralimanohar, Naveen Jouppi, Norm Balasubramonian, Rajeev
Abstract	A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor perfor- mance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire mod- els (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache Access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies. Keywords: cache models, non-uniform cache archi- tectures (NUCA), memory hierarchies, on-chip intercon- nects.
Starting Page	3
Ending Page	14
Page Count	12
File Format	PDF
ISBN	0769530478
ISSN	10724451
DOI	10.1109/MICRO.2007.30
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-12-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in