NDLI: Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Process Variation Tolerant 3T1D-Based Cache Architectures

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Optimal versus Heuristic Global Code Scheduling

Global Multi-Threaded Instruction Scheduling

Revisiting the Sequential Programming Model for Multi-Core

Penelope: The NBTI-Aware Processor

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

Self-calibrating Online Wearout Detection

Implementing Signatures for Transactional Memory

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Impact of Cache Coherence Protocols on the Processing of Network Traffic

Flattened Butterfly Topology for On-Chip Networks

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Leveraging 3D Technology for Improved Reliability

Effective Optimistic-Checker Tandem Core Design through Architectural Pruning

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach

Informed Microarchitecture Design Space Exploration Using Workload Dynamics

Time Interpolation: So Many Metrics, So Few Registers

Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications

A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy

Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors

A Framework for Providing Quality of Service in Chip Multi-Processors

A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

Composable Lightweight Processors

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

Scavenger: A New Last Level Cache Architecture with Global Block Priority

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache

Emulating Optimal Replacement with a Shepherd Cache

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Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

Content Provider	ACM Digital Library
Author	Chu, Michael Ravindran, Rajiv Mahlke, Scott
Abstract	The recent design shift towards multicore processors has spawned a significant amount of research in the area of program paralleliza- tion. The future abundance of cores on a single chip requires pro- grammer and compiler intervention to increase the amount of par- allel work possible. Much of the recent work has fallen into the areas of coarse-grain parallelization: new programming models and different ways to exploit threads and data-level parallelism. This work focuses on a complementary direction, improving per- formance through automated fine-grain parallelization. The main difficulty in achieving a performance benefit from fine-grain paral- lelism is the distribution of data memory accesses across the data caches of each core. Poor choices in the placement of data ac- cesses can lead to increased memory stalls and low resource utiliza- tion. We propose a profile-guided method for partitioning mem- ory accesses across distributed data caches. First, a profile deter- mines affinity relationships between memory accesses and work- ing set characteristics of individual memory operations in the pro- gram. Next, a program-level partitioning of the memory opera- tions is performed to divide the memory accesses across the data caches. As a result, the data accesses are proactively dispersed to reduce memory stalls and improve computation parallelization. A final detailed partitioning of the computation instructions is per- formed with knowledge of the cache location of their associated data. Overall, our data partitioning reduces stall cycles by up to 51% versus data-incognizant partitioning, and has an overall speedup average of 30% over a single core processor.
Starting Page	369
Ending Page	380
Page Count	12
File Format	PDF
ISBN	0769530478
ISSN	10724451
DOI	10.1109/MICRO.2007.11
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-12-01
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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