NDLI: Compact modeling of carbon nanotube transistor for early stage process-design exploration

Please wait, while we are loading the content...

Compact modeling of carbon nanotube transistor for early stage process-design exploration

Energy efficient near-threshold chip multi-processing

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs

Towards a software approach to mitigate voltage emergencies

A process variation aware low power synthesis methodology for fixed-point FIR filters

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

Throughput of multi-core processors under thermal constraints

Low power soft-output signal detector design for wireless MIMO communication systems

A 0.4-V UWB baseband processor

A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices

Vibration energy scavenging and management for ultra low power applications

A 65-nm pulsed latch with a single clocked transistor

Nanotechnology for low-power and high-speed nanoelectronics applications

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Analysis of dynamic voltage/frequency scaling in chip-multiprocessors

A robust edge encoding technique for energy-efficient multi-cycle interconnect

Power optimal MTCMOS repeater insertion for global buses

Improving disk reuse for reducing power consumption

Voltage- and ABB-island optimization in high level synthesis

A low-power SRAM using bit-line charge-recycling technique

Dynamic voltage frequency scaling for multi-tasking systems using online learning

A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices

Resource area dilation to reduce power density in throughput servers

High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control

Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source

A methodology for analysis and verification of power gated circuits with correlated results

Low power FPGA design using hybrid CMOS-NEMS approach

Evaluating design tradeoffs in on-chip power management for CMPs

Low-power process-variation tolerant arithmetic units using input-based elastic clocking

Timing-driven row-based power gating

PVS: passive voltage scaling for wireless sensor networks

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies

Minimizing power dissipation during write operation to register files

Thermal-aware task scheduling at the system software level

An architecture for energy efficient sphere decoding

Locality-driven architectural cache sub-banking for leakage energy reduction

A micro power management system and maximum output power control for solar energy harvesting applications

Design of an efficient power delivery network in an soc to enable dynamic power management

$V_{t}$ balancing and device sizing towards high yield of sub-threshold static logic gates

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

Sleep transistor sizing and control for resonant supply noise damping

Detailed placement for leakage reduction using systematic through-pitch variation

A programming environment with runtime energy characterization for energy-aware applications

Power signal processing: a new perspective for power analysis and optimization

An on-chip NBTI sensor for measuring PMOS threshold voltage degradation

Thermal response to DVFS: analysis with an Intel Pentium M

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing

A multi-model power estimation engine for accuracy optimization

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Energy-efficient and performance-enhanced disks using flash-memory cache

Power-efficient LDPC code decoder architecture

Clocking structures and power analysis for nanomagnet-based logic devices

A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches

Thermal-aware methodology for repeater insertion in low-power VLSI circuits

Early power grid verification under circuit current uncertainties

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules

Low-power H.264/AVC baseline decoder for portable applications

Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system

SAPP: scalable and adaptable peak power management in nocs

A low-power CSCD asynchronous viterbi decoder for wireless applications

Future of on-chip interconnection architectures

The parallel computing landscape: a Berkeley view

All watts considered

Reducing cache energy consumption by tag encoding in embedded processors

On reducing energy-consumption by late-inserting instructions into the issue queue

Power-aware operand delivery

On the latency, energy and area of checkpointed, superscalar register alias tables

Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

Electromigration and voltage drop aware power grid optimization for power gated ICs

Reducing display power in DVS-enabled handheld systems

Multicasting based topology generation and core mapping for a power efficient networks-on-chip

Phase-aware adaptive hardware selection for power-efficient scientific computations

Signoff power methodology for contactless smartcards

An ilp based approach to reducing energy consumption in nocbased CMPS

Compact modeling of carbon nanotube transistor for early stage process-design exploration

Content Provider	ACM Digital Library
Author	Balijepalli, Asha Cao, Yu Sinha, Saurabh
Abstract	Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process and design conditions, such as diameter, chirality, gate dielectrics, and bias voltages. With the physical modeling of the contact, this model covers both the Schottky-barrier CNT (SB-CNT) and MOS-type CNT. The proposed model does not require any iteration and thus, significantly enhances the simulation efficiency to support large-scale design research. Using this model, we benchmark the performance of a FO4 inverter with CNT and 22nm CMOS technology. The following key insights are extracted: (1) even with the SB-CNT and realistic layout parasitics, the circuit speed can be more than 10X that of 22nm CMOS; (2) The diameter range of 1-1.5nm exhibits the maximum tolerance to contact materials and process variations; (3) a CNT circuit allows better scaling of the supply voltage (Vdd) for power reduction. For a fixed energy consumption and Vdd, the CNT speed is 4X that of 22nm CMOS. Overall, the new model enables efficient design research with CNT, revealing tremendous opportunities for both high-speed and low-power applications.
Starting Page	2
Ending Page	7
Page Count	6
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283783
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-08-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Optimum delay Cnt Process variability Modeling Schottky-barrier Surface potential
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in