NDLI: Multicasting based topology generation and core mapping for a power efficient networks-on-chip

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Multicasting based topology generation and core mapping for a power efficient networks-on-chip

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Multicasting based topology generation and core mapping for a power efficient networks-on-chip

Content Provider	ACM Digital Library
Author	Vemuri, Ranga Sethuraman, Balasubramanian
Abstract	Networks-on-Chip (NoC) is an emerging alternative for system integration that is projected to meet the growing communication demands for future System-on-Chips. Compared to the bus-based systems, traditional NoCs do not have versatile data transfer capabilities like broadcasting. $Multi^{2}$ Router is a Multi Local Port Router (MLPR) architecture that has multicast feature in-built inside the router elements of an MLPR-based NoC. In this research,we present an NoC configuration generation approach exploiting the multicast feature. Compared to the traditional single port based unicast transfers, we observe an average of 50% packet reduction (maximum of 74% using 9 Local Port (LP) router, in benchmark p3), across a set of benchmarks. On an average, when compared to the traditional 1 LP unicast router, there is a 16% reduction in the execution time and 35% reduction (maximum of 67% in benchmark p4) in total power consumption. The results show the promise of the proposed scheme, and thus, help to realize power-efficient Networks-on-Chip.
Starting Page	399
Ending Page	402
Page Count	4
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283868
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-08-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicast Power-efficient core mapping Mesh topology Networks-on-chip Packet reduction
Content Type	Text
Resource Type	Article

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