NDLI: Low-power process-variation tolerant arithmetic units using input-based elastic clocking

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Low-power process-variation tolerant arithmetic units using input-based elastic clocking

Content Provider	ACM Digital Library
Author	Mohapatra, Debabrata Roy, Kaushik Karakonstantis, Georgios
Abstract	In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.
Starting Page	74
Ending Page	79
Page Count	6
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283797
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-08-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Process tolerant Elastic clocking Low power
Content Type	Text
Resource Type	Article

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