NDLI: Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

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Compact modeling of carbon nanotube transistor for early stage process-design exploration

Energy efficient near-threshold chip multi-processing

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs

Towards a software approach to mitigate voltage emergencies

A process variation aware low power synthesis methodology for fixed-point FIR filters

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

Throughput of multi-core processors under thermal constraints

Low power soft-output signal detector design for wireless MIMO communication systems

A 0.4-V UWB baseband processor

A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices

Vibration energy scavenging and management for ultra low power applications

A 65-nm pulsed latch with a single clocked transistor

Nanotechnology for low-power and high-speed nanoelectronics applications

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Analysis of dynamic voltage/frequency scaling in chip-multiprocessors

A robust edge encoding technique for energy-efficient multi-cycle interconnect

Power optimal MTCMOS repeater insertion for global buses

Improving disk reuse for reducing power consumption

Voltage- and ABB-island optimization in high level synthesis

A low-power SRAM using bit-line charge-recycling technique

Dynamic voltage frequency scaling for multi-tasking systems using online learning

A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices

Resource area dilation to reduce power density in throughput servers

High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control

Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source

A methodology for analysis and verification of power gated circuits with correlated results

Low power FPGA design using hybrid CMOS-NEMS approach

Evaluating design tradeoffs in on-chip power management for CMPs

Low-power process-variation tolerant arithmetic units using input-based elastic clocking

Timing-driven row-based power gating

PVS: passive voltage scaling for wireless sensor networks

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies

Minimizing power dissipation during write operation to register files

Thermal-aware task scheduling at the system software level

An architecture for energy efficient sphere decoding

Locality-driven architectural cache sub-banking for leakage energy reduction

A micro power management system and maximum output power control for solar energy harvesting applications

Design of an efficient power delivery network in an soc to enable dynamic power management

$V_{t}$ balancing and device sizing towards high yield of sub-threshold static logic gates

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

Sleep transistor sizing and control for resonant supply noise damping

Detailed placement for leakage reduction using systematic through-pitch variation

A programming environment with runtime energy characterization for energy-aware applications

Power signal processing: a new perspective for power analysis and optimization

An on-chip NBTI sensor for measuring PMOS threshold voltage degradation

Thermal response to DVFS: analysis with an Intel Pentium M

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing

A multi-model power estimation engine for accuracy optimization

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Energy-efficient and performance-enhanced disks using flash-memory cache

Power-efficient LDPC code decoder architecture

Clocking structures and power analysis for nanomagnet-based logic devices

A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches

Thermal-aware methodology for repeater insertion in low-power VLSI circuits

Early power grid verification under circuit current uncertainties

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules

Low-power H.264/AVC baseline decoder for portable applications

Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system

SAPP: scalable and adaptable peak power management in nocs

A low-power CSCD asynchronous viterbi decoder for wireless applications

Future of on-chip interconnection architectures

The parallel computing landscape: a Berkeley view

All watts considered

Reducing cache energy consumption by tag encoding in embedded processors

On reducing energy-consumption by late-inserting instructions into the issue queue

Power-aware operand delivery

On the latency, energy and area of checkpointed, superscalar register alias tables

Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

Electromigration and voltage drop aware power grid optimization for power gated ICs

Reducing display power in DVS-enabled handheld systems

Multicasting based topology generation and core mapping for a power efficient networks-on-chip

Phase-aware adaptive hardware selection for power-efficient scientific computations

Signoff power methodology for contactless smartcards

An ilp based approach to reducing energy consumption in nocbased CMPS

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

Content Provider	ACM Digital Library
Editor	Keshavarzi, Ali Raghunathan, Anand Davoodi, Azadeh Lu, Zhijian Massoud, Yehia Poncino, Massimo Li, William Fallah, Farzan Bhunia, Swarup Henkel, Joerg Cao, Yu Narayanan, Vijaykrishnan Wu, Qing Marculescu, Diana Mukhopadhay, Saibal Chiprout, Eli Yang, Jun Mahadev, Nemani Kursun, Volkan Zhang, Ron Kim, Chris Pandya, Gunjan Otis, Brian Leenaerts, Domine Chakrabarti, Chaitali Chen, Yiran Yeap, Geoffrey Lu, Yung-Hsiang
Copyright Year	2007
Abstract	The 2007 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to Portland, Oregon also known as "The City of Roses" in the beautiful Pacific Northwest region of the USA. On par with this great location, a strong and diverse technical program features three invited talks from leaders in the field, a special session and embedded tutorials. On the first day, Robert Chau, Senior Fellow, Intel Corporation, will deliver the keynote on nanotechnology for low-power and high-speed nanoelectronics applications. The afternoon session on Monday will feature an invited special session on the future of on-chip interconnection architectures with presentations from Shekhar Borkar, Fellow, Intel Corporation and Bill Dally, Stanford University. The first plenary talk on Tuesday will feature David Patterson from UC Berkeley. His talk will address the parallel computing landscape from the perspective of ongoing research efforts at Berkeley. The second plenary talk on Wednesday will be delivered by Luiz Barroso, Distinguished Engineer, Google, on power consumption issues in server machines. Out of 192 submissions received from 14 countries, 74 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 30% for regular and short papers (57 papers), or 39% including 17 posters. Topics range from low power technology, circuits, and memory; low voltage analog and RF design; power aware design and tools; power efficient architecture techniques; and system and application level power optimization. The program is organized in twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as one interactive poster session that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. The program also includes an industry session that will highlight contributions showcased by companies participating in the ISLPED exhibits. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session.
Related Links	http://computer.org/proceedings/islped/2007/3709
ISBN	9781595937094
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-08-27
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

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