NDLI: Locality-driven architectural cache sub-banking for leakage energy reduction

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Locality-driven architectural cache sub-banking for leakage energy reduction

Content Provider	ACM Digital Library
Author	Golubeva, Olga Loghi, Mirko Poncino, Massimo Macii, Enrico
Abstract	In most processors, caches account for the largest fraction of onchip transistors, thus being a primary candidate for tackling the leakage problem. Existing architectural solutions usually rely on customized cache structures, which are needed to implement some kind of power management policy. Memory arrays, however, are carefully developed and finely tuned by foundries, and their internal structure is typically non accessible to system designers. In this work, we focus on the reduction of leakage energy in caches, without interfering with its internal design. We proposed a truly architectural solution that is based on cache sub-banking and on the detection and mapping of the application localities, detected from a profiling of the cache access patterns. By customizing the mapping between the application address space and the cache, we can expose as much address space idleness as possible, thus resulting in shutdown potential which allows significant leakage saving. Results show leakage energy reduction of up to 48% (about 30% on average), with marginal impact on miss rate or execution time.
Starting Page	274
Ending Page	279
Page Count	6
File Format	PDF
ISBN	9781595937094
DOI	10.1145/1283780.1283839
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-08-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Memory hierarchy Banked cache Architectural optimization Leakage reduction
Content Type	Text
Resource Type	Article

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