NDLI: Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

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Towards truly integrated photonic and electronic computing

Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

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Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

Content Provider	ACM Digital Library
Author	Muntimadugu, Kirthi Krishna Palem, Krishna V. Lingamneni, Avinash Piguet, Christian Enz, Christian Karp, Richard M.
Abstract	Owing to a growing desire to reduce energy consumption and widely anticipated hurdles to the continued technology scaling promised by Moore's law, techniques and technologies such as inexact circuits and probabilistic CMOS (PCMOS) have gained prominence. These radical approaches trade accuracy at the hardware level for significant gains in energy consumption, area, and speed. While holding great promise, their ability to influence the broader milieu of computing is limited due to two shortcomings. First, they were mostly based on ad-hoc hand designs and did not consider algorithmically well-characterized automated design methodologies. Also, existing design approaches were limited to particular layers of abstraction such as physical, architectural and algorithmic or more broadly software. However, it is well-known that significant gains can be achieved by optimizing across the layers. To respond to this need, in this paper, we present an algorithmically well-founded cross-layer co-design framework (CCF) for automatically designing inexact hardware in the form of datapath elements. Specifically adders and multipliers, and show that significant associated gains can be achieved in terms of energy, area, and delay or speed. Our algorithms can achieve these gains with adding any additional hardware overhead. The proposed CCF framework embodies a symbiotic relationship between architecture and logic-layer design through the technique of probabilistic pruning combined with the novel confined voltage scaling technique introduced in this paper, applied at the physical layer. A second drawback of the state of the art with inexact design is the lack of physical evidence established through measuring fabricated ICs that the gains and other benefits that can be achieved are valid. Again, in this paper, we have addressed this shortcoming by using CCF to fabricate a prototype chip implementing inexact data-path elements; a range of 64-bit integer adders whose outputs can be erroneous. Through physical measurements of our prototype chip wherein the inexact adders admit expected relative error magnitudes of 10% or less, we have found that cumulative gains over comparable and fully accurate chips, quantified through the area-delay-energy product, can be a multiplicative factor of 15 or more. As evidence of the utility of these results, we demonstrate that despite admitting error while achieving gains, images processed using the FFT algorithm implemented using our inexact adders are visually discernible.
Starting Page	3
Ending Page	12
Page Count	10
File Format	PDF
ISBN	9781450312158
DOI	10.1145/2212908.2212912
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Inexact circuit design Cross-layer co-design framework Energy-accuracy tradeoff Probabilistic pruning Average case analysis Confined voltage scaling Error-resilient systems
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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