NDLI: A hierachical configuration system for a massively parallel neural hardware platform

Please wait, while we are loading the content...

Towards truly integrated photonic and electronic computing

Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

Mesh independent loop fusion for unstructured mesh applications

SuperCoP: a general, correct, and performance-efficient supervised memory system

Studying the impact of application-level optimizations on the power consumption of multi-core architectures

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching

Reuse distance based performance modeling and workload mapping

An out-of-order vector processing mechanism for multimedia applications

Learning, evolution and adaptation in racing games

CRESTA: a software focussed approach to exascale co-design

A reconfigurable optical/electrical interconnect architecture for large-scale clusters and datacenters

GA-GPU: extending a library-based global address spaceprogramming model for scalable heterogeneouscomputing systems

Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies

Improving energy efficiency for mobile platforms by exploiting low-power sleep states

Adaptive task duplication using on-line bottleneck detection for streaming applications

The boat hull model: enabling performance prediction for parallel computing prior to code development

Towards player-driven procedural content generation

Game AI revisited

TERAFLUX: exploiting dataflow parallelism in teradevices

BSArc: blacksmith streaming architecture for HPC accelerators

SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection

The tradeoffs of fused memory hierarchies in heterogeneous computing architectures

Improving coherence protocol reactiveness by trading bandwidth for latency

Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture

Parameterized micro-benchmarking: an auto-tuning approach for complex applications

An efficient vectorization of linked-cell particle simulations

Towards more intelligent adaptive video game agents: a computational intelligence perspective

DEEP: an exascale prototype architecture based on a flexible configuration

A limits study of benefits from nanostore-based future data-centric system architectures

Architectural support of multiple hypervisors over single platform for enhancing cloud computing security

DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories

A hierachical configuration system for a massively parallel neural hardware platform

A flexible OS-based approach for characterizing solid-state disk endurance

Dynamic percolation: a case of study on the shortcomings of traditional optimization in many-core architectures

How AI can change the way we play games

Mont-Blanc: towards energy-efficient HPC systems

CoreSymphony architecture

Instructions activating conditions for hardware-based auto-scheduling

Selective search of inlining vectors for program optimization

$D^{3}AS$ project: a different approach to the manycore challenges

A capacity-efficient insertion policy for dynamic cache resizing mechanisms

Accelerated high-performance computing through efficient multi-process GPU resource sharing

Improving the performance of k-means clustering through computation skipping and data locality optimizations

A hierachical configuration system for a massively parallel neural hardware platform

Content Provider	ACM Digital Library
Author	Rast, Alexander Plana, Luis A. Davies, Sergio Sharp, Thomas Galluppi, Francesco Furber, Steve
Abstract	Simulation of large networks of neurons is a powerful and increasingly prominent methodology for investigate brain functions and structures. Dedicated parallel hardware is a natural candidate for simulating the dynamic activity of many non-linear units communicating asynchronously. It is only scientifically useful, however, if the simulation tools can be configured and run easily and quickly. We present a method to map network models to computational nodes on the SpiNNaker system, a programmable parallel neurally-inspired hardware architecture, by exploiting the hierarchies built in the model. This PArtitioning and Configuration MANager (PACMAN) system supports arbitrary network topologies and arbitrary membrane potential and synapse dynamics, and (most importantly) decouples the model from the device, allowing a variety of languages (PyNN, Nengo, etc.) to drive the simulation hardware. Model representation operates on a Population/Projection level rather than a single-neuron and connection level, exploiting hierarchical properties to lower the complexity of allocating resources and mapping the model onto the system. PACMAN can be thus be used to generate structures coming from different models and front-ends, either with a host-based process, or by parallelising it on the SpiNNaker machine itself to speed up the generation process greatly. We describe the approach with a first implementation of the framework used to configure the current generation of SpiNNaker machines and present results from a set of key benchmarks. The system allows researchers to exploit dedicated simulation hardware which may otherwise be difficult to program. In effect, PACMAN provides automated hardware acceleration for some commonly used network simulators while also pointing towards the advantages of hierarchical configuration for large, domain-specific hardware systems.
Starting Page	183
Ending Page	192
Page Count	10
File Format	PDF
ISBN	9781450312158
DOI	10.1145/2212908.2212934
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Spinnaker Spiking neural networks Neuromorphic hardware Parallel hardware
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Parallelization of Neural Processing on Neuromorphic Hardware

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Algorithm and software for simulation of spiking neural networks on the multi-chip spinnaker system (2010)

Using Stochastic Spiking Neural Networks on SpiNNaker to Solve Constraint Satisfaction Problems

Neuromorphic Robotic Platform with Visual Input, Processor and Actuator, Based on Spiking Neural Networks

Beyond LIF Neurons on Neuromorphic Hardware

Classification and regression of spatio-temporal signals using NeuCube and its realization on SpiNNaker neuromorphic hardware

Structural Plasticity on the SpiNNaker Many-Core Neuromorphic System

Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system (2010)

A hierachical configuration system for a massively parallel neural hardware platform

Similar Documents

Parallelization of Neural Processing on Neuromorphic Hardware

Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware

Algorithm and software for simulation of spiking neural networks on the multi-chip spinnaker system (2010)

Using Stochastic Spiking Neural Networks on SpiNNaker to Solve Constraint Satisfaction Problems

Neuromorphic Robotic Platform with Visual Input, Processor and Actuator, Based on Spiking Neural Networks

Beyond LIF Neurons on Neuromorphic Hardware

Classification and regression of spatio-temporal signals using NeuCube and its realization on SpiNNaker neuromorphic hardware

Structural Plasticity on the SpiNNaker Many-Core Neuromorphic System

Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system (2010)

A hierachical configuration system for a massively parallel neural hardware platform