NDLI: Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles

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Clock domain crossing aware sequential clock gating

Online binding of applications to multiple clock domains in shared FPGA-based systems

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems

Automatic extraction of assertions from execution traces of behavioural models

Low-cost checkpointing in automotive safety-relevant systems

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs

Reliable information extraction for single trace attacks

Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis

SelectDirectory: a selective directory for cache coherence in many-core architectures

Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking

Delay analysis of structural real-time workload

Error recovery in digital microfluidics for personalized medicine

High-resolution online power monitoring for modern microprocessors

Privacy-preserving functional IP verification utilizing fully homomorphic encryption

An online thermal-constrained task scheduler for 3D multi-core processors

Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory

Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach

A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems

Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI

Improved practical differential fault analysis of grain-128

Exploiting DRAM restore time variations in deep sub-micron scaling

Coherent crosstalk noise analyses in ring-based optical interconnects

Sufficient response time analysis considering dependencies between rate-dependent tasks

On the statistical memory architecture exploration and optimization

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Comparison of multi-purpose cores of Keccak and AES

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Asymmetric underlapped FinFET based robust SRAM design at 7nm node

A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters

DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS

Adaptive on-the-fly application performance modeling for many cores

Computing approximately, and efficiently

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Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting

Axilog: language support for approximate hardware design

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

STT MRAM-Based PUFs

HLC: software-based half-level-cell flash memory

A thermal stress-aware algorithm for power and temperature management of MPSoCs

DSP based programmable FHD HEVC decoder

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Efficient bit error rate estimation for high-speed link by Bayesian model fusion

Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machine

Transparent acceleration of program execution using reconfigurable hardware

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation

Optimization of quantum computer architecture using a resource-performance simulator

Dynamic power and performance back-annotation for fast and accurate functional hardware simulation

Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications

Quick error detection tests with fast runtimes for effective post-silicon validation and debug

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Models for deterministic execution of real-time multiprocessor applications

Tackling the bottleneck of delay tables in 3D ultrasound imaging

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems

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An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes

Profiling-driven multi-cycling in FPGA high-level synthesis

Formal analysis of the startup delay of SOME/IP service discovery

A methodology for automated design of embedded bit-flips detectors in post-silicon validation

Uncertainty-aware reliability analysis and optimization

Path selection based acceleration of conditionals in CGRAs

Scandalee: a side-channel-based disassembler using local electromagnetic emanations

Interplay of loop unrolling and multidimensional memory partitioning in HLS

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes

A fast parallel sparse solver for SPICE-based circuit simulators

Effective verification of low-level software with nested interrupts

A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors

Efficient software implementation of ring-LWE encryption

A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving

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Timing analysis of an avionics case study on complex hardware/software platforms

Temperature-aware software-based self-testing for delay faults

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell

A score-based classification method for identifying hardware-trojans at gate-level netlists

Adaptively tolerate power-gating-induced power/ground noise under process variations

Enabling vertical wormhole switching in 3D NoC-bus hybrid systems

Engine control: task modeling and analysis

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system

On-line prediction of NBTI-induced aging rates

A robust authentication methodology using physically unclonable functions in DRAM arrays

Quality configurable reduce-and-rank for energy efficient approximate computing

Eliminating intra-warp conflict misses in GPU

A small non-volatile write buffer to reduce storage writes in smartphones

Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints

Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles

New testing procedure for finding insertion sites of stealthy hardware trojans

$d^{2}-LBDR:$ distance-driven routing to handle permanent failures in 2D mesh NOCs

Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior

A scan partitioning algorithm for reducing capture power of delay-fault LBIST

Spiking neural network with RRAM: can we use it for real-world application?

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI

AHEAD: automated framework for hardware accelerated iterative data analysis

Predictive dynamic thermal and power management for heterogeneous mobile platforms

Accelerating complex brain-model simulations on GPU platforms

Giant spin hall effect (GSHE) logic design for low power application

Fast deployment of alternate analog test using Bayesian model fusion

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Accelerating arithmetic kernels with coherent attached FPGA coprocessors

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GPU-accelerated small delay fault simulation

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Power minimization for data center with guaranteed QoS

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Statistical library characterization using belief propagation across multiple technology nodes

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Approximate associative memristive memory for energy-efficient GPUs

Distributed reinforcement learning for power limited many-core system performance optimization

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Formal verification of sequential Galois field arithmetic circuits using algebraic geometry

Simultaneous transistor pairing and placement for CMOS standard cells

Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation

Integrated CMOS receiver for wearable coil arrays in MRI applications

Race to idle or not: balancing the memory sleep time with DVS for energy minimization

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Analysis of ethernet-switch traffic shapers for in-vehicle networking applications

Data mining diagnostics and bug MRIs for HW bug localization

Efficient soft error vulnerability estimation of complex designs

Hardware-assisted code obfuscation for FPGA soft microprocessors

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SODA: software defined FPGA based accelerators for big data

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Transparent linking of compiled software and synthesized hardware

Initial transient response of oscillators with long settling time

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Formal probabilistic analysis of distributed dynamic thermal management

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M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors

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Fault-based attacks on the Bel-T block cipher family

Dynamic reconfigurable puncturing for secure wireless communication

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Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation

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Minimum current consumption transition time optimization methodology for low power CTS

On the premises and prospects of timing speculation

QR-decomposition architecture based on two-variable numeric function approximation

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Feature selection for alternate test using wrappers: application to an RF LNA case study

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Impact of interconnect multiple-patterning variability on SRAMs

In-place memory mapping approach for optimized parallel hardware interleaver architectures

Improving SIMD code generation in QEMU

Logical equivalence checking of asynchronous circuits using commercial tools

An approximate voting scheme for reliable computing

Coherence based message prediction for optically interconnected chip multiprocessors

Maximizing common idle time on multi-core processors with shared memory

Reuse distance analysis for locality optimization in loop-dominated applications

May-happen-in-parallel analysis of ESL models using UPPAAL model checking

FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design

OpenMP and timing predictability: a possible union?

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TAPP: temperature-aware application mapping for NoC-based many-core processors

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A unified hardware/software MPSoC system construction and run-time framework

SAHARA: a security-aware hazard and risk analysis method

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors

Malleable NoC: dark silicon inspired adaptable Network-on-Chip

Spintastic: spin-based stochastic logic for energy-efficient computing

$(AS)^{2}:$ accelerator synthesis using algorithmic skeletons for rapid design space exploration

Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation

Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores

Topology identification for smart cells in modular batteries

Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique

Assisted generation of frame conditions for formal models

Occupancy detection via iBeacon on Android devices for smart building management

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LVS check for photonic integrated circuits: curvilinear feature extraction and validation

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FP-scheduling for mode-controlled dataflow: a case study

Timing verification for adaptive integrated circuits

Fast and accurate branch predictor simulation

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Ageing simulation of analogue circuits and systems using adaptive transient evaluation

A robust approach for process variation aware mask optimization

Comparative study of test generation methods for simulation accelerators

Analog neuromorphic computing enabled by multi-gate programmable resistive devices

A tool for the assisted design of charge redistribution SAR ADCs

FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing

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Detection of asymmetric aging-critical voltage conditions in analog power-down mode

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NFRs early estimation through software metrics

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains

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Optimizing dynamic trace signal selection using machine learning and linear programming

Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles

Content Provider	ACM Digital Library
Author	Upfal, Eli Arumugam, Guru Prakash Augustine, John Srikanthan, Prashanth Bhargava, Ayush Palem, Krishna Yenugula, Sreelatha
Abstract	It is increasingly accepted that energy savings can be achieved by trading the accuracy of a computing system for energy gains---quite often significantly. This approach is referred to as inexact or approximate computing. Given that a significant portion of the energy in a modern general purpose processor is spent on moving data to and from storage, and that increasingly data movement contributes significantly to activity during the execution of applications, it is important to be able to develop techniques and methodologies for inexact computing in this context. To accomplish this to its fullest level, it is important to start with algorithmic specifications and alter their intrinsic design to take advantage of inexactness. This calls for a new approach to inexact memory aware algorithm design (IMAD) or co-design. In this paper, we provide the theoretical foundations which include novel models as well as technical results in the form of upper and lower bounds for IMAD in the context of universally understood and canonical problems: variations of sorting, and string matching. Surprisingly, IMAD allowed us to design entirely error-free algorithms while achieving energy gain factors of 1.5 and 5 in the context of sorting and string matching when compared to their traditional (textbook) algorithms. IMAD is also amenable to theoretical analysis and we present several asymptotic bounds on energy gains.
Starting Page	752
Ending Page	757
Page Count	6
File Format	PDF
ISBN	9783981537048
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-09
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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