NDLI: The tradeoffs of fused memory hierarchies in heterogeneous computing architectures

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The tradeoffs of fused memory hierarchies in heterogeneous computing architectures

Content Provider	ACM Digital Library
Author	Spafford, Kyle L. Meredith, Jeremy S. Li, Dong Roth, Philip C. Vetter, Jeffrey S. Lee, Seyong
Abstract	With the rise of general purpose computing on graphics processing units (GPGPU), the influence from consumer markets can now be seen across the spectrum of computer architectures. In fact, many of the high-ranking Top500 HPC systems now include these accelerators. Traditionally, GPUs have connected to the CPU via the PCIe bus, which has proved to be a significant bottleneck for scalable scientific applications. Now, a trend toward tighter integration between CPU and GPU has removed this bottleneck and unified the memory hierarchy for both CPU and GPU cores. We examine the impact of this trend for high performance scientific computing by investigating AMD's new Fusion Accelerated Processing Unit (APU) as a testbed. In particular, we evaluate the tradeoffs in performance, power consumption, and programmability when comparing this unified memory hierarchy with similar, but discrete GPUs.
Starting Page	103
Ending Page	112
Page Count	10
File Format	PDF
ISBN	9781450312158
DOI	10.1145/2212908.2212924
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Heterogeneous Apu Performance analysis Gpgpu
Content Type	Text
Resource Type	Article

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