NDLI: Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture

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Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture

Content Provider	ACM Digital Library
Author	Palumbo, Francesca Pani, Danilo Congiu, Andrea Raffo, Luigi
Abstract	Massively Parallel Systems-on-chip represent the new frontier of integrated computing systems for general purpose computing. The integration of a huge number of cores poses several issues such as the efficiency and flexibility of the interconnection network in order to serve in the best way the different traffic patterns that can arise. In this paper we present the CYBER architecture, an advanced Network-on-Chip (NoC) for concurrent hybrid switching with prioritized best effort Quality of Service. Compared to similar architectures, CYBER allows the simultaneous exploitation of packet switching and circuit switching, providing two different priorities to packets in order to be able to transmit urgent messages (e.g. signalling) while long-lasting transactions and huge packets congestion are present. In terms of the typical NoC metrics, evaluated on synthetic traffic representative of several application categories, their standard trend is degraded while serving both circuit and packet switching simultaneously but the architecture preserves a predictable behaviour. A CMOS 90nm implementation reveals a maximum operating frequency of about 1GHz.
Starting Page	173
Ending Page	182
Page Count	10
File Format	PDF
ISBN	9781450312158
DOI	10.1145/2212908.2212933
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-15
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Hybrid switching Noc Qos Mpsoc Prioritized best effort
Content Type	Text
Resource Type	Article

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