NDLI: A New Approach to Automatic Memory Banking using Trace-Based Address Mining

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A New Approach to Automatic Memory Banking using Trace-Based Address Mining

Content Provider	ACM Digital Library
Author	Zhang, Zhiru Al-Hawaj, Khalid Musa Zhou, Yuan
Abstract	Recent years have seen an increased deployment of FPGAs as programmable accelerators for improving the performance and energy efficiency of compute-intensive applications. A well-known "secret sauce" of achieving highly efficient FPGA acceleration is to create application-specific memory architecture that fully exploits the vast amounts of on-chip memory bandwidth provided by the reconfigurable fabric. In particular, memory banking is widely employed when multiple parallel memory accesses are needed to meet a demanding throughput constraint. In this paper we propose TraceBanking, a novel and flexible trace-driven address mining algorithm that can automatically generate efficient memory banking schemes by analyzing a stream of memory address bits. Unlike mainstream memory partitioning techniques that are based on static compile-time analysis, TraceBanking only relies on simple source-level instrumentation to provide the memory trace of interest without enforcing any coding restrictions. More importantly, our technique can effectively handle memory traces that exhibit either affine or non-affine access patterns, and produce efficient banking solutions with a reasonable runtime. Furthermore, TraceBanking can be used to process a reduced memory trace with the aid of an SMT prover to verify if the resulting banking scheme is indeed conflict free. Our experiments on Xilinx FPGAs show that TraceBanking achieves competitive performance and resource usage compared to the state-of-the-art across a set of real-life benchmarks with affine memory accesses. We also perform a case study on a face detection algorithm to show that TraceBanking is capable of generating a highly area-efficient memory partitioning based on a sequence of addresses without any obvious access patterns.
Starting Page	179
Ending Page	188
Page Count	10
File Format	PDF
ISBN	9781450343541
DOI	10.1145/3020078.3021734
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpgas High-level synthesis Compiler optimization Reconfigurable computing Combinatorial optimization Data mining Memory systems
Content Type	Text
Resource Type	Article

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