NDLI: ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

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OLAF'17: Third International Workshop on Overlay Architectures for FPGAs

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ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

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ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

Content Provider	ACM Digital Library
Author	Hu, Yiming Mao, Huizi Yang, Huazhong Yao, Song Kang, Junlong Luo, Hong Li, Xin Li, Yubin Xie, Dongliang Han, Song Wang, Yu Dally, William Bill J.
Abstract	Long Short-Term Memory (LSTM) is widely used in speech recognition. In order to achieve higher prediction accuracy, machine learning scientists have built increasingly larger models. Such large model is both computation intensive and memory intensive. Deploying such bulky model results in high power consumption and leads to a high total cost of ownership (TCO) of a data center. To speedup the prediction and make it energy efficient, we first propose a load-balance-aware pruning method that can compress the LSTM model size by 20x (10x from pruning and 2x from quantization) with negligible loss of the prediction accuracy. The pruned model is friendly for parallel processing. Next, we propose a scheduler that encodes and partitions the compressed model to multiple PEs for parallelism and schedule the complicated LSTM data flow. Finally, we design the hardware architecture, named Efficient Speech Recognition Engine (ESE) that works directly on the sparse LSTM model. Implemented on Xilinx KU060 FPGA running at 200MHz, ESE has a performance of 282 GOPS working directly on the sparse LSTM network, corresponding to 2.52 TOPS on the dense one, and processes a full LSTM for speech recognition with a power dissipation of 41 Watts. Evaluated on the LSTM for speech recognition benchmark, ESE is 43x and 3x faster than Core i7 5930k CPU and Pascal Titan X GPU implementations. It achieves 40x and 11.5x higher energy efficiency compared with the CPU and GPU respectively.
Starting Page	75
Ending Page	84
Page Count	10
File Format	PDF
ISBN	9781450343541
DOI	10.1145/3020078.3021745
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Deep learning Fpga Speech recognition Software-hardware co-design Model compression Hardware acceleration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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