NDLI: Scala Based FPGA Design Flow (Abstract Only)

Please wait, while we are loading the content...

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs

An OpenCL™ Deep Learning Accelerator on Arria 10

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping

FPGAs in the Cloud

Hardware Synthesis of Weakly Consistent C Concurrency

Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search

Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center

FPGA Acceleration for Computational Glass-Free Displays

Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only)

Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only)

FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only)

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Synchronization Constraints for Interconnect Synthesis

Automatic Construction of Program-Optimized FPGA Memory Networks

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

A New Approach to Automatic Memory Banking using Trace-Based Address Mining

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture

Energy Efficient Scientific Computing on FPGAs using OpenCL

Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling

A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)

Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only)

Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only)

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

FPGA-Accelerated Transactional Execution of Graph Workloads

Secure Function Evaluation Using an FPGA Overlay Architecture

A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only)

Accelerating Financial Market Server through Hybrid List Design (Abstract Only)

ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only)

Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis

Scala Based FPGA Design Flow (Abstract Only)

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)

RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only)

Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules

Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only)

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)

GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only)

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

A Machine Learning Framework for FPGA Placement (Abstract Only)

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only)

Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only)

CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only)

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)

Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only)

Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only)

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only)

Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only)

fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only)

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)

An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only)

Scala Based FPGA Design Flow (Abstract Only)

Content Provider	ACM Digital Library
Author	Li, Yao Lai, Meng Xiong, Weilun Liu, Yanqiang Qi, Zhengwei Chen, Cheng Guan, Haibing
Abstract	With the rapid growth of data scale, data analysis applications start to meet the performance bottleneck, and thus requiring the aid of hardware acceleration. At the same time, Field Programmable Gate Arrays (FPGAs), known for their high customizability and parallel nature, have gained momentum in the past decade. However, the efficiency of development for acceleration system based on FPGAs is severely constrained by the traditional languages and tools, due to their deficiency in expressibility, extendability, limited libraries and semantic gap between software and hardware design. This paper proposes a new open-source DSL based hardware design framework called VeriScala (https://github.com/VeriScala/VeriScala) that supports highly abstracted object-oriented hardware defining, programmatical testing, and interactive on-chip debugging. By adopting DSL embedded in Scala, we introduce modern software developing concepts into hardware designing including object-oriented programming, parameterized types, type safety, test automation, etc. VeriScala enables designers to describe their hardware designs in Scala, generate Verilog code automatically and interactively debug and test hardware design in real FPGA environment. Through the evaluation on real world applications and usability test, we show that VeriScala provides a practical approach for rapid prototyping of hardware acceleration systems. (This work is supported by the National Key Research & Development Program of China 2016YFB1000500).
Starting Page	286
Ending Page	286
Page Count	1
ISBN	9781450343541
DOI	10.1145/3020078.3021762
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Veriscala Dsl
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Novel Method for Enabling FPGA Context-Switch (Abstract Only)

An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only)

Scala for introductory CS and parallelism(abstract only)

A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only)

Energy-efficient FPGA interconnect architecture design (abstract only)

Using Scala strategically across the undergraduate curriculum (abstract only)

Regular fabric for regular FPGA (abstract only)

A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)

Parallel FPGA placement based on individual LUT placement (abstract only)

Scala Based FPGA Design Flow (Abstract Only)

Similar Documents

A Novel Method for Enabling FPGA Context-Switch (Abstract Only)

An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only)

Scala for introductory CS and parallelism(abstract only)

A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only)

Energy-efficient FPGA interconnect architecture design (abstract only)

Using Scala strategically across the undergraduate curriculum (abstract only)

Regular fabric for regular FPGA (abstract only)

A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)

Parallel FPGA placement based on individual LUT placement (abstract only)

Scala Based FPGA Design Flow (Abstract Only)