NDLI: A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)

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A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)

Content Provider	ACM Digital Library
Author	Wei, Zhiqiang Li, Jing Zha, Yue Zhang, Jialiang
Abstract	This poster presents a data-centric reconfigurable architecture, which is enabled by emerging non-volatile memory, i.e., RRAM. Compared to the heterogeneous architecture of commercial FPGAs, it is inherently a homogeneous architecture comprising of a two-dimensional (2D) array of mixed-signal processing "tiles". Each tile can be configured into one or a combination of the four modes: logic, memory, TCAM, and interconnect. Computation within a tile is performed in analog domain for energy efficiency, whereas communication between tiles is performed in digital domain for resilience. Such flexibility allows users to partition resources based on applications' needs, in contrast to fixed hardware design using dedicated hard IP blocks in FPGAs. In addition to better resource usage, its "memory friendly" architecture effectively addressed the limitations of commercial FPGAs i.e., scarce on-chip memory resources, making it an effective complement to FPGAs. Moreover, its coarse-grained configuration results in shallower logic depth, less inter-tile routing overhead, and thus smaller area and better performance, compared with its FPGA counter part. Our preliminary study shows great promise of this architecture for improving performance, energy efficiency and security.
Starting Page	285
Ending Page	285
Page Count	1
ISBN	9781450343541
DOI	10.1145/3020078.3021759
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Non-volatile memory Ternary content addressable memory Mixed-signal processing Coarse-grained configuration Reconfigurable architecture
Content Type	Text
Resource Type	Article

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