NDLI: GenerateRCS: A high-level design tool for generating reconfigurable computing systems

Content Provider	IEEE Xplore Digital Library
Author	Gohringer, D. Luhmann, J. Becker, J.
Copyright Year	2009
Description	Author affiliation: ITIV, Universität Karlsruhe (TH), Germany (Becker, J.) \|\| FGAN-FOM, Ettlingen, Germany (Gohringer, D.; Luhmann, J.)
Abstract	The traditional design flow for run-time reconfigurable hardware systems is very time-consuming until today. There exist some tools alleviating the generation of reconfigurable systems, but none of them provides a seamless high-level design flow decreasing the threshold of acceptance for the non-specialist in reconfigurable hardware. Most of these tools focus on the placement of the reconfigurable modules and their interfaces as well as on the generation of the partial bitstreams, but none of them focus on the required high-level transformations, such as for example the automatic instantiation of communication interfaces in the HDL-file. In this paper a tool called GenerateRCS is presented, which provides a graphical user interface (GUI) for an easy system integration on reconfigurable hardware. Furthermore, it can be used to grapically view the components, signals and parameters of a VHDL-file. GenerateRCS can be integrated into high-level tools such as Xilinx Embedded Development Kit (EDK). This way, reconfigurable computing systems can be generated very fast and without the need to write HDL -code.
Starting Page	159
Ending Page	164
File Size	536103
Page Count	6
File Format	PDF
ISBN	9781457702372
e-ISBN	9781457702365
DOI	10.1109/VLSISOC.2009.6041347
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-12
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGAs Dynamic and Partial Reconfiguration Reconfigurable Computing Design Flow
Content Type	Text
Resource Type	Article

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