NDLI: Hardware Synthesis of Weakly Consistent C Concurrency

Please wait, while we are loading the content...

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs

An OpenCL™ Deep Learning Accelerator on Arria 10

Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping

FPGAs in the Cloud

Hardware Synthesis of Weakly Consistent C Concurrency

Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search

Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center

FPGA Acceleration for Computational Glass-Free Displays

Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only)

Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only)

FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only)

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Synchronization Constraints for Interconnect Synthesis

Automatic Construction of Program-Optimized FPGA Memory Networks

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation

A New Approach to Automatic Memory Banking using Trace-Based Address Mining

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture

Energy Efficient Scientific Computing on FPGAs using OpenCL

Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling

A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)

Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only)

Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only)

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis

FPGA-Accelerated Transactional Execution of Graph Workloads

Secure Function Evaluation Using an FPGA Overlay Architecture

A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only)

Accelerating Financial Market Server through Hybrid List Design (Abstract Only)

ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only)

Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network

120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board

Accelerating Face Detection on Programmable SoC Using C-Based Synthesis

Scala Based FPGA Design Flow (Abstract Only)

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)

RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only)

Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System

Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules

Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only)

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)

GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only)

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

A Machine Learning Framework for FPGA Placement (Abstract Only)

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only)

Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only)

CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only)

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)

Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only)

Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only)

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only)

Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only)

fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)

Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only)

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)

An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only)

Hardware Synthesis of Weakly Consistent C Concurrency

Content Provider	ACM Digital Library
Author	Constantinides, George A. Ramanathan, Nadesh Wickerson, John Fleming, Shane T.
Abstract	Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via fine-grained atomic operations ('atomics'), have been shown empirically to be the fastest class of multi-threaded algorithms in the realm of conventional processors. This paper explores how these algorithms can be compiled from C to reconfigurable hardware via high-level synthesis (HLS). We focus on the scheduling problem, in which software instructions are assigned to hardware clock cycles. We first show that typical HLS scheduling constraints are insufficient to implement atomics, because they permit some instruction reorderings that, though sound in a single-threaded context, demonstrably cause erroneous results when synthesising multi-threaded programs. We then show that correct behaviour can be restored by imposing additional intra-thread constraints among the memory operations. We implement our approach in the open-source LegUp HLS framework, and provide both sequentially consistent (SC) and weakly consistent ('weak') atomics. Weak atomics necessitate fewer constraints than SC atomics, but suffice for many concurrent algorithms. We confirm, via automatic model-checking, that we correctly implement the semantics defined by the 2011 revision of the C standard. A case study on a circular buffer suggests that circuits synthesised from programs that use atomics can be 2.5x faster than those that use locks, and that weak atomics can yield a further 1.5x speedup.
Starting Page	169
Ending Page	178
Page Count	10
File Format	PDF
ISBN	9781450343541
DOI	10.1145/3020078.3021733
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	C/c++ Fpgas Atomic operations High-level synthesis Lock-free algorithms Memory consistency models Scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Concurrency-Aware Thread Scheduling for High-Level Synthesis

A Case for Work-stealing on FPGAs with OpenCL Atomics

Lock-Free Algorithms under Stochastic Schedulers

Prove Once, Run Efficiently Anywhere: Tools for Lock-free Concurrent Algorithms

High-level synthesis using genetic algorithms for dynamically reconfigurable FPGAs

Automatically comparing memory consistency models

Lock-free consistency control for web 2.0 applications

A versatile STM protocol with invisible read operations that satisfies the virtual world consistency condition

On the Consistency Conditions of Transactional Memories

Hardware Synthesis of Weakly Consistent C Concurrency

Similar Documents

Concurrency-Aware Thread Scheduling for High-Level Synthesis

A Case for Work-stealing on FPGAs with OpenCL Atomics

Lock-Free Algorithms under Stochastic Schedulers

Prove Once, Run Efficiently Anywhere: Tools for Lock-free Concurrent Algorithms

High-level synthesis using genetic algorithms for dynamically reconfigurable FPGAs

Automatically comparing memory consistency models

Lock-free consistency control for web 2.0 applications

A versatile STM protocol with invisible read operations that satisfies the virtual world consistency condition

On the Consistency Conditions of Transactional Memories

Hardware Synthesis of Weakly Consistent C Concurrency