NDLI: Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

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Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Content Provider	ACM Digital Library
Author	Seo, Jae-sun Vrudhula, Sarma Cao, Yu Ma, Yufei
Abstract	As convolution layers contribute most operations in convolutional neural network (CNN) algorithms, an effective convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN accelerator. Convolution in CNNs involves three-dimensional multiply and accumulate (MAC) operations with four levels of loops, which results in a large design space. Prior works either employ limited loop optimization techniques, e.g. loop unrolling, tiling and interchange, or only tune some of the design variables after the accelerator architecture and dataflow are already fixed. Without fully studying the convolution loop optimization before the hardware design phase, the resulting accelerator can hardly exploit the data reuse and manage data movement efficiently. This work overcomes these barriers by quantitatively analyzing and optimizing the design objectives (e.g. required memory access) of the CNN accelerator based on multiple design variables. We systematically explore the trade-offs of hardware cost by searching the design variable configurations, and propose a specific dataflow of hardware CNN acceleration to minimize the memory access and data movement while maximizing the resource utilization to achieve high performance. The proposed CNN acceleration scheme and architecture are demonstrated on a standalone Altera Arria 10 GX 1150 FPGA by implementing end-to-end VGG-16 CNN model and achieved 645.25 GOPS of throughput and 47.97 ms of latency, which is a >3.2× enhancement compared to state-of-the-art FPGA implementations of VGG model.
Starting Page	45
Ending Page	54
Page Count	10
File Format	PDF
ISBN	9781450343541
DOI	10.1145/3020078.3021736
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Convolutional neural networks Hardware acceleration
Content Type	Text
Resource Type	Article

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