NDLI: RESP: a robust physical unclonable function retrofitted into embedded SRAM array

Please wait, while we are loading the content...

Mapping on multi/many-core systems: survey of current and emerging trends

Double patterning lithography-aware analog placement

Dynamic behavior of cell signaling networks: model design and analysis automation

Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance

Balancing security and utility in medical devices?

Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Improving energy gains of inexact DSP hardware through reciprocative error compensation

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

GPU-based n-detect transition fault ATPG

Predicting future technology performance

Proactive circuit allocation in multiplane NoCs

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition

Cross-layer racetrack memory design for ultra high density and low power consumption

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique

ABCD-L: approximating continuous linear systems using boolean models

Machine-learning-based hotspot detection using topological classification and critical feature extraction

Automatic clustering of wafer spatial signatures

Cloud platforms and embedded computing: the operating systems of the future

Role of power grid in side channel attack and power-grid-aware secure design

Lighting the dark silicon by exploiting heterogeneity on future processors

Scalable vectorless power grid current integrity verification

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

21st century digital design tools

System architecture and software design for electric vehicles

Reliable on-chip systems in the nano-era: lessons learnt and future trends

Power benefit study for ultra-high density transistor-level monolithic 3D ICs

Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints

Verifying SystemC using an intermediate verification language and symbolic simulation

The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers

Towards structured ASICs using polarity-tunable Si nanowire transistors

A novel analytical method for worst case response time estimation of distributed embedded systems

CoARX: a coprocessor for ARX-based cryptographic algorithms

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog

FPGA code accelerators - the compiler perspective

Can CAD cure cancer?

Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching

Taming the complexity of coordinated place and route

Exploration with upgradeable models using statistical methods for physical model emulation

Power gating applied to MP-SoCs for standby-mode power management

Underpowering NAND flash: profits and perils

Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCC

HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors

On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery

On the convergence of mainstream and mission-critical markets

Workload and user experience-aware dynamic reliability management in multicore processors

Simultaneous analog placement and routing with current flow and current density considerations

An efficient and effective analytical placer for FPGAs

Towards trustworthy medical devices and body area networks

Exploiting program-level masking and error propagation for constrained reliability optimization

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Stitch-aware routing for multiple e-beam lithography

Post-silicon conformance checking with virtual prototypes

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies

A heterogeneous multiple network-on-chip design: an application-aware approach

LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric

Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures

Improving the energy efficiency of hardware-assisted watchpoint systems

RESP: a robust physical unclonable function retrofitted into embedded SRAM array

Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

A novel fuzzy matching model for lithography hotspot detection

Multidimensional analog test metrics estimation using extreme value theory and statistical blockade

Tessellation: refactoring the OS around explicit resource containers with continuous adaptation

NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters

Simultaneous multithreading support in embedded distributed memory MPSoCs

Constraint abstraction for vectorless power grid verification

Smart non-default routing for clock power reduction

Model-based development and verification of control software for electric vehicles

A layout-based approach for multiple event transient analysis

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Relax-and-retime: a methodology for energy-efficient recovery based design

Handling design and implementation optimizations in equivalence checking for behavioral synthesis

Sacha: the Stanford carbon nanotube controlled handshaking robot

Optimizations for configuring and mapping software pipelines in many core systems

Reconfigurable pipelined coprocessor for multi-mode communication transmission

A new time-stepping method for circuit simulation

Let's put the car in your phone!

Integrated instruction cache analysis and locking in multitasking real-time systems

Routability-driven placement for hierarchical mixed-size circuit designs

Modular system-level architecture for concurrent cell balancing

Power management and delivery for high-performance microprocessors

New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices

Distributed run-time resource management for malleable applications on many-core platforms

Hierarchical power management for asymmetric multi-core in dark silicon era

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Liveness evaluation of a cyclo-static DataFlow graph

Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits

Throughput-oriented kernel porting onto FPGAs

Low-energy encryption for medical devices: security adds an extra design dimension

REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs

Automatic design rule correction in presence of multiple grids and track patterns

On testing timing-speculative circuits

The ITRS design technology and system drivers roadmap: process and status

Designing energy-efficient NoC for real-time embedded systems through slack optimization

Pareto epsilon-dominance and identifiable solutions for BioCAD modeling

Synthesis of feedback decoders for initialized encoders

Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

VeriTrust: verification for hardware trust

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

An efficient layout decomposition approach for triple patterning lithography

High-throughput TSV testing and characterization for 3D integration using thermal mapping

The autonomic operating system research project: achievements and future directions

High-performance hardware monitors to protect network processors from data plane attacks

APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation

The impact of electromigration in copper interconnects on power grid integrity

Routing congestion estimation with real design constraints

Hybrid energy storage systems and battery management for electric vehicles

Quantitative evaluation of soft error injection techniques for robust system design

Minimum-energy state guided physical design for nanomagnet logic

Post-placement voltage island generation for timing-speculative circuits

A counterexample-guided interpolant generation algorithm for SAT-based model checking

Electrical artificial skin using ultraflexible organic transistor

A scenario-based run-time task mapping algorithm for MPSoCs

Accelerators for biologically-inspired attention and recognition

Time-domain segmentation based massively parallel simulation for ADCs

The undetectable and unprovable hardware trojan horse

Precise timing analysis for direct-mapped caches

Ripple 2.0: high quality routability-driven placement via global router integration

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

Flexible on-chip power delivery for energy efficient heterogeneous systems

SAW: system-assisted wear leveling on the write endurance of NAND flash devices

netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor

An accurate semi-analytical framework for full-chip TSV-induced stress modeling

Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine

Memory partitioning for multidimensional arrays in high-level synthesis

Polyhedral model based mapping optimization of loop nests for CGRAs

Towards variation-aware system-level power estimation of DRAMs: an empirical approach

Multiple chip planning for chip-interposer codesign

An ATE assisted DFD technique for volume diagnosis of scan chains

RISO: relaxed network-on-chip isolation for cloud processors

Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations

On learning-based methods for design-space exploration with high-level synthesis

Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system

On effective and efficient in-field TSV repair for stacked 3D ICs

Compiler-based side channel vulnerability analysis and optimized countermeasures application

An optimized page translation for mobile virtualization

TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Reliability challenges for electric vehicles: from devices to architecture and systems software

Efficiently tolerating timing violations in pipelined microprocessors

Ultra low power associative computing with spin neurons and resistive crossbar memory

Analysis and characterization of inherent application resilience for approximate computing

A robust constraint solving framework for multiple constraint sets in constrained random verification

Non-volatile FPGAs based on spintronic devices

Early exploration for platform architecture instantiation with multi-mode application partitioning

Stochastic circuits for real-time image-processing applications

A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics

Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power

SSDM: smart stack data management for software managed multicores (SMMs)

Optimization of placement solutions for routability

DMR3D: dynamic memory relocation in 3D multicore systems

Power and signal integrity challenges in 3D systems

Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection design

Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems

Techniques for energy-efficient power budgeting in data centers

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization

Smart hill climbing for agile dynamic mapping in many-core systems

Gene modification identification under flux capacity uncertainty

Runtime dependency analysis for loop pipelining in high-level synthesis

Improving charging efficiency with workload scheduling in energy harvesting embedded systems

Hierarchical decoding of double error correcting codes for high speed reliable memories

Understanding the trade-offs in multi-level cell ReRAM memory design

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Simulation knowledge extraction and reuse in constrained random processor verification

Relays do not leak: CMOS does

DuraCache: a durable SSD cache using MLC NAND flash

On robust task-accurate performance estimation

Temperature aware thread block scheduling in GPGPUs

InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits

HCI-tolerant NoC router microarchitecture

A field-programmable pin-constrained digital microfluidic biochip

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Creation of ESL power models for communication architectures using automatic calibration

Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier

Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

Single-photon image sensors

Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture

Improving PUF security with regression-based distiller

RESP: a robust physical unclonable function retrofitted into embedded SRAM array

Content Provider	ACM Digital Library
Author	Bhunia, Swarup Hashemian, Maryam S. Zheng, Yu
Abstract	Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues in Integrated Circuits (ICs). A majority of existing PUFs rely on a dedicated circuit structure for generating chip-specific signatures, which often imposes concerns due to area/power overhead and extra design efforts. Furthermore, existing PUF-based signature generation cannot be employed to authenticate chips already in the market. In this paper, we propose RESP, a novel PUF structure realized in embedded SRAM array, a prevalent component in processors and system-on-chips (SOCs), with virtually no design modification. RESP leverages on voltage-depend memory access failures (during write) to produce large volume of high-quality challenge-response pairs. Since many modern ICs integrate SRAM array of varying size with isolated power grid, RESP can be easily retrofitted into these chips. Circuit-level simulation of 1000 chips using realistic process variation model shows high uniqueness of 49.2% average inter-die Hamming distance and good reproducibility of 2.88% intra-die Hamming distance under temperature < 85°C. The device aging effect, e.g. bias temperature instability (BTI), results in only 4.95% estimated unstable bits for ten-year usage.
Starting Page	1
Ending Page	9
Page Count	9
File Format	PDF
ISBN	9781450320719
DOI	10.1145/2463209.2488807
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-29
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Puf Hardware security Bti Signature Sram
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in