NDLI: Designing energy-efficient NoC for real-time embedded systems through slack optimization

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Designing energy-efficient NoC for real-time embedded systems through slack optimization

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Designing energy-efficient NoC for real-time embedded systems through slack optimization

Content Provider	ACM Digital Library
Author	Ouyang, Jin Xie, Yuan Zhan, Jia Thiele, Lothar Stoimenov, Nikolay Narayanan, Vijaykrishnan
Abstract	Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to minimize the energy consumption of NoC without violating the pre-specified latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline---the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450320719
DOI	10.1145/2463209.2488780
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-29
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Network calculus Network-on-chip Voltage-frequency scaling
Content Type	Text
Resource Type	Article

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