NDLI: Aging-aware compiler-directed VLIW assignment for GPGPU architectures

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Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Content Provider	ACM Digital Library
Author	Benini, Luca Gupta, Rajesh K. Rahimi, Abbas
Abstract	Negative bias temperature instability (NBTI) adversely affects the reliability of a processor by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across functional units and instructions: some are affected more (hence less reliable) than others. This paper proposes a NBTI-aware compiler-directed very long instruction word (VLIW) assignment scheme that uniformly distributes the stress of instructions with the aim of minimizing aging of GPGPU architecture without any performance penalty. The proposed solution is an entirely software technique based on static workload characterization and online execution with NBTI monitoring that equalizes the expected lifetime of each processing element by regenerating aging-aware healthy kernels that respond to the specific health state of GPGPU. We demonstrate our approach on AMD Evergreen architecture where iso-throughput executions of the healthy kernels reduce NBTI-induced voltage threshold shift up to 49% (11%) compared to naïve kernel executions, with (without) architectural support for power-gating. The kernel adaption flow takes average of 13 millisecond on a typical host machine thus making it suitable for practical implementation.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450320719
DOI	10.1145/2463209.2488754
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-29
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Dynamic binary optimizer Vliw Adaptive kernel Nbti Aging-aware compilation Gpgpu
Content Type	Text
Resource Type	Article

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