NDLI: High-performance hardware monitors to protect network processors from data plane attacks

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Mapping on multi/many-core systems: survey of current and emerging trends

Double patterning lithography-aware analog placement

Dynamic behavior of cell signaling networks: model design and analysis automation

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Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Improving energy gains of inexact DSP hardware through reciprocative error compensation

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

GPU-based n-detect transition fault ATPG

Predicting future technology performance

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Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

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ABCD-L: approximating continuous linear systems using boolean models

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High-performance hardware monitors to protect network processors from data plane attacks

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Hierarchical decoding of double error correcting codes for high speed reliable memories

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Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

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High-performance hardware monitors to protect network processors from data plane attacks

Content Provider	ACM Digital Library
Author	Tessier, Russell Chandrikakutty, Harikrishnan Unnikrishnan, Deepak Wolf, Tilman
Abstract	The Internet represents an essential communication infrastructure that needs to be protected from malicious attacks. Modern network routers are typically implemented using embedded multi-core network processors that are inherently vulnerable to attack. Hardware monitor subsystems, which can verify the behavior of a router's packet processing system at runtime, can be used to identify and respond to an ever-changing range of attacks. While hardware monitors have primarily been described in the context of general-purpose computing, our work focuses on two important aspects that are relevant to the embedded networking domain: We present the design and prototype implementation of a high-performance monitor that can track each processor instruction with low memory overhead. Additionally, our monitor is capable of defending against attacks on processors with a Harvard architecture, the dominant contemporary network processor organization. We demonstrate that our monitor architecture provides no network slowdown in the absence of an attack and provides the capability to drop attack packets without otherwise affecting regular network traffic when an attack occurs.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450320719
DOI	10.1145/2463209.2488832
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-29
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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