NDLI: Exploration with upgradeable models using statistical methods for physical model emulation

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Mapping on multi/many-core systems: survey of current and emerging trends

Double patterning lithography-aware analog placement

Dynamic behavior of cell signaling networks: model design and analysis automation

Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance

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Aging-aware compiler-directed VLIW assignment for GPGPU architectures

Improving energy gains of inexact DSP hardware through reciprocative error compensation

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

GPU-based n-detect transition fault ATPG

Predicting future technology performance

Proactive circuit allocation in multiplane NoCs

Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition

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ABCD-L: approximating continuous linear systems using boolean models

Machine-learning-based hotspot detection using topological classification and critical feature extraction

Automatic clustering of wafer spatial signatures

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Role of power grid in side channel attack and power-grid-aware secure design

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Scalable vectorless power grid current integrity verification

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21st century digital design tools

System architecture and software design for electric vehicles

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FPGA code accelerators - the compiler perspective

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Taming the complexity of coordinated place and route

Exploration with upgradeable models using statistical methods for physical model emulation

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Post-silicon conformance checking with virtual prototypes

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LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric

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Routability-driven placement for hierarchical mixed-size circuit designs

Modular system-level architecture for concurrent cell balancing

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New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices

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Hierarchical power management for asymmetric multi-core in dark silicon era

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

Liveness evaluation of a cyclo-static DataFlow graph

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Throughput-oriented kernel porting onto FPGAs

Low-energy encryption for medical devices: security adds an extra design dimension

REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)

XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs

Automatic design rule correction in presence of multiple grids and track patterns

On testing timing-speculative circuits

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Quantitative evaluation of soft error injection techniques for robust system design

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Accelerators for biologically-inspired attention and recognition

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Precise timing analysis for direct-mapped caches

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A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

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SAW: system-assisted wear leveling on the write endurance of NAND flash devices

netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems

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Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine

Memory partitioning for multidimensional arrays in high-level synthesis

Polyhedral model based mapping optimization of loop nests for CGRAs

Towards variation-aware system-level power estimation of DRAMs: an empirical approach

Multiple chip planning for chip-interposer codesign

An ATE assisted DFD technique for volume diagnosis of scan chains

RISO: relaxed network-on-chip isolation for cloud processors

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On learning-based methods for design-space exploration with high-level synthesis

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RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system

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Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

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Efficiently tolerating timing violations in pipelined microprocessors

Ultra low power associative computing with spin neurons and resistive crossbar memory

Analysis and characterization of inherent application resilience for approximate computing

A robust constraint solving framework for multiple constraint sets in constrained random verification

Non-volatile FPGAs based on spintronic devices

Early exploration for platform architecture instantiation with multi-mode application partitioning

Stochastic circuits for real-time image-processing applications

A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics

Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power

SSDM: smart stack data management for software managed multicores (SMMs)

Optimization of placement solutions for routability

DMR3D: dynamic memory relocation in 3D multicore systems

Power and signal integrity challenges in 3D systems

Performance enhancement of garbage collection for flash storage devices: an efficient victim block selection design

Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems

Techniques for energy-efficient power budgeting in data centers

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization

Smart hill climbing for agile dynamic mapping in many-core systems

Gene modification identification under flux capacity uncertainty

Runtime dependency analysis for loop pipelining in high-level synthesis

Improving charging efficiency with workload scheduling in energy harvesting embedded systems

Hierarchical decoding of double error correcting codes for high speed reliable memories

Understanding the trade-offs in multi-level cell ReRAM memory design

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Simulation knowledge extraction and reuse in constrained random processor verification

Relays do not leak: CMOS does

DuraCache: a durable SSD cache using MLC NAND flash

On robust task-accurate performance estimation

Temperature aware thread block scheduling in GPGPUs

InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits

HCI-tolerant NoC router microarchitecture

A field-programmable pin-constrained digital microfluidic biochip

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Creation of ESL power models for communication architectures using automatic calibration

Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier

Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems

Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation

Single-photon image sensors

Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture

Improving PUF security with regression-based distiller

Exploration with upgradeable models using statistical methods for physical model emulation

Content Provider	ACM Digital Library
Author	Vahid, Frank Miller, Bailey Givargis, Tony
Abstract	Physical models capture environmental phenomena such as biochemical reactions, a beating heart, or neuron synapses, using mathematical equations. Previous work has shown that physical models can execute orders of magnitude faster on FPGAs (Field-Programmable Gate Arrays) compared to desktop PCs. Different models of the same physical phenomenon may vary, with "upgraded" models being more accurate but using more FPGA area and having slower performance. We propose that design space exploration considering upgradable models can dramatically increase the useful design space. We present an analysis of the solution space for utilizing networks of processing-elements (PEs) on FPGAs to emulate physical models, implement a web-based frontend to a compiler and cycle-accurate simulator of PE networks to estimate solution metrics, and utilize design-of-experiments (DOE) statistical methods to identify Pareto points. By considering upgradeable models during the design space exploration of a human lung physical model, the solution space of possible speedup, area, and accuracy is increased by 6X, 7.3X, and 1.5X, respectively, compared to evaluating a single model.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450320719
DOI	10.1145/2463209.2488925
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-05-29
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Cyber-physical systems Design space exploration
Content Type	Text
Resource Type	Article

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