NDLI: Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design

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Dynamically reconfigurable hybrid cache: an energy-efficient last-level cache design

Content Provider	ACM Digital Library
Author	Potkonjak, Miodrag Cong, Jason Liu, Bin Huang, Hui Liu, Chunyue Chen, Yu-Ting Reinman, Glenn
Abstract	The recent development of non-volatile memory (NVM), such as spin-torque transfer magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of low leakage and high density, provides an energy-efficient alternative to traditional SRAM in cache systems. We propose a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM. RHC can be reconfigured by powering on/off SRAM/NVM arrays in a way-based manner. In this work, we discuss both the architecture and circuit design issues for RHC. Furthermore, we provide hardware-based mechanisms to dynamically reconfigure RHC on-the-fly based on the cache demand. Experimental results on a wide range of benchmarks show that the proposed RHC achieves an average 63%, 48% and 25% energy saving over non-reconfigurable SRAM-based cache, non-reconfigurable hybrid cache, and reconfigurable SRAM-based cache, while maintaining the system performance (at most 4% performance overhead).
Starting Page	45
Ending Page	50
Page Count	6
File Format	PDF
ISBN	9783981080186
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-03-12
Publisher Place	San Jose
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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